Effective Timing Error Tolerance in Flip-Flop Based Core Designs
Timing errors turn to be a great concern in nanometer technology integrated circuits. This work presents a low-cost and power efficient, multiple timing error detection and correction technique for flip-flop based core designs. Two new flip-flop designs are introduced, which exploit a transition det...
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| Veröffentlicht in: | Journal of electronic testing 2013-12, Vol.29 (6), p.795-804 |
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| container_title | Journal of electronic testing |
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| creator | Valadimas, Stefanos Tsiatouhas, Yiorgos Arapoyanni, Angela Xarchakos, Petros |
| description | Timing errors turn to be a great concern in nanometer technology integrated circuits. This work presents a low-cost and power efficient, multiple timing error detection and correction technique for flip-flop based core designs. Two new flip-flop designs are introduced, which exploit a transition detector for timing error detection along with asynchronous local error correction schemes to provide timing error tolerance. The proposed, the Razor and the Time Dilation techniques were applied separately in the design of three versions of a 32-bit MIPS microprocessor core and the pci_bridge32 IWLS05 core, using a 90 nm CMOS technology. Comparisons based on simulation results validate the efficiency of the new design approach. |
| doi_str_mv | 10.1007/s10836-013-5419-3 |
| format | Article |
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| subjects | CAE) and Design Circuits and Systems CMOS Computer-Aided Engineering (CAD Design engineering Electrical Engineering Engineering Fault tolerance Integrated circuits Nanotechnology Studies |
| title | Effective Timing Error Tolerance in Flip-Flop Based Core Designs |
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