On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation

The paper proposes an integrated methodology to abstract already existing heterogeneous IPs into SysML behavioral equivalent models. This approach aims at integrating the abstracted components with partially specified platforms at SysML level and verifying their integration. During the abstraction flow, the level of details can be chosen according to the needs of the designer. They are related to communication and synchronization protocols, hierarchical structure, and data types of the abstracted IPs and the details about continuous flows to be abstracted in SysML. Therefore, the generated SysML models can preserve information about structure in combination with the functional description for continuous and discrete behaviors and, thus, they can be synthesized into C++ or modeling tools like Matlab Simulink. This can be used to verify the integration of the so generated models exploiting simulation based techniques. The main benefit of the proposed methodology is relieving designers from the modeling time and error risks especially for those designs in which the SysML model of the architecture is particularly structured and detailed. The approach has been fully integrated and extended to support also components with analogic behaviors. The proposed framework has been applied positively to different benchmarks in order to be validated. Three case studies are presented in order to better understand the approach applicability and effectiveness.