A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip

This paper presents a deadlock-free fault-tolerant routing algorithm for irregular mesh network-on-chips based on a region-based approach. In this approach, a set of rectangular faulty regions called faulty blocks is formed for faulty nodes and a detour path is defined for each faulty block to indic...

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Veröffentlicht in:Journal of electronic testing 2013-06, Vol.29 (3), p.415-429
Hauptverfasser: Fukushima, Yusuke, Fukushi, Masaru, Yairi, Ikuko Eguchi
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Fukushi, Masaru
Yairi, Ikuko Eguchi
description This paper presents a deadlock-free fault-tolerant routing algorithm for irregular mesh network-on-chips based on a region-based approach. In this approach, a set of rectangular faulty regions called faulty blocks is formed for faulty nodes and a detour path is defined for each faulty block to indicate how packets must detour thefaulty block. The most recent routing algorithm on this approach is Message-Route (Holsmark and Kumar J Inf Sci Eng 23:1649–1662, 2007 ) which does not have restrictions on the number of tolerable faulty nodes and its distribution. However, this algorithm has three crucial problems; (1) this algorithm fails to provide complete and deadlock-free routing, (2) many nonfaulty nodes are contained in faulty blocks and thus deactivated, and (3) complex routing functions are not feasible for hardware implementation. In this paper, we give a solution for each of the above three problems. We correct the errors of Message-Route to make it complete and deadlock-free. Then, we propose a deadlock-free fault-tolerant routing algorithm which can work under small-sized faulty blocks with a simple routing control. Experimental results show that the proposed algorithm significantly reduces the size of faulty blocks and improves communication latency for both random and cluster faults. Moreover, an FPGA implementation of the proposed algorithm is also discussed.
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fullrecord <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_1417913868</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>3012976181</sourcerecordid><originalsourceid>FETCH-LOGICAL-c415t-2c6b967c8977f558c93cd3d134b2744fc99f1ad746ea78af47a6690a53f03e023</originalsourceid><addsrcrecordid>eNp1kEtLAzEURoMoWKs_wF3AjZtoXpPHslSrBR9Q6jqkaWY6dTqpyQzivzdlXIjg6m7O-bgcAC4JviEYy9tEsGICYcJQwaRE-giMSCEZwpLKYzDCmjKkiOSn4CylLc4OLcQILCdw4as6tGhlk1_Dme2bDi1D46NtO7gIfVe3FZw0VYh1t9mVIUJ6B-cx-qpvbITPPm3gi-8-Q3xHeWa6qffn4KS0TfIXP3cM3mb3y-kjenp9mE8nT8hxUnSIOrHSQjqlpSyLQjnN3JqtCeMrKjkvndYlsWvJhbdS2ZJLK4TGtmAlZh5TNgbXw-4-ho_ep87s6uR809jWhz4ZwonUhCmhMnr1B92GPrb5O0OYVphpKkimyEC5GFKKvjT7WO9s_DIEm0NnM3Q2ubM5dDY6O3RwUmbbysdfy_9K31kNfmc</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1398039261</pqid></control><display><type>article</type><title>A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip</title><source>SpringerLink Journals - AutoHoldings</source><creator>Fukushima, Yusuke ; Fukushi, Masaru ; Yairi, Ikuko Eguchi</creator><creatorcontrib>Fukushima, Yusuke ; Fukushi, Masaru ; Yairi, Ikuko Eguchi</creatorcontrib><description>This paper presents a deadlock-free fault-tolerant routing algorithm for irregular mesh network-on-chips based on a region-based approach. In this approach, a set of rectangular faulty regions called faulty blocks is formed for faulty nodes and a detour path is defined for each faulty block to indicate how packets must detour thefaulty block. The most recent routing algorithm on this approach is Message-Route (Holsmark and Kumar J Inf Sci Eng 23:1649–1662, 2007 ) which does not have restrictions on the number of tolerable faulty nodes and its distribution. However, this algorithm has three crucial problems; (1) this algorithm fails to provide complete and deadlock-free routing, (2) many nonfaulty nodes are contained in faulty blocks and thus deactivated, and (3) complex routing functions are not feasible for hardware implementation. In this paper, we give a solution for each of the above three problems. We correct the errors of Message-Route to make it complete and deadlock-free. Then, we propose a deadlock-free fault-tolerant routing algorithm which can work under small-sized faulty blocks with a simple routing control. Experimental results show that the proposed algorithm significantly reduces the size of faulty blocks and improves communication latency for both random and cluster faults. Moreover, an FPGA implementation of the proposed algorithm is also discussed.</description><identifier>ISSN: 0923-8174</identifier><identifier>EISSN: 1573-0727</identifier><identifier>DOI: 10.1007/s10836-013-5377-9</identifier><language>eng</language><publisher>Boston: Springer US</publisher><subject>Algorithms ; CAE) and Design ; Circuits and Systems ; Clusters ; Computer networks ; Computer-Aided Engineering (CAD ; Electrical Engineering ; Electronics ; Engineering ; Fault tolerance ; Faults ; Hardware ; Integrated circuits ; Routing ; Routing (telecommunications)</subject><ispartof>Journal of electronic testing, 2013-06, Vol.29 (3), p.415-429</ispartof><rights>Springer Science+Business Media New York 2013</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c415t-2c6b967c8977f558c93cd3d134b2744fc99f1ad746ea78af47a6690a53f03e023</citedby><cites>FETCH-LOGICAL-c415t-2c6b967c8977f558c93cd3d134b2744fc99f1ad746ea78af47a6690a53f03e023</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/s10836-013-5377-9$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://link.springer.com/10.1007/s10836-013-5377-9$$EHTML$$P50$$Gspringer$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,41488,42557,51319</link.rule.ids></links><search><creatorcontrib>Fukushima, Yusuke</creatorcontrib><creatorcontrib>Fukushi, Masaru</creatorcontrib><creatorcontrib>Yairi, Ikuko Eguchi</creatorcontrib><title>A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip</title><title>Journal of electronic testing</title><addtitle>J Electron Test</addtitle><description>This paper presents a deadlock-free fault-tolerant routing algorithm for irregular mesh network-on-chips based on a region-based approach. In this approach, a set of rectangular faulty regions called faulty blocks is formed for faulty nodes and a detour path is defined for each faulty block to indicate how packets must detour thefaulty block. The most recent routing algorithm on this approach is Message-Route (Holsmark and Kumar J Inf Sci Eng 23:1649–1662, 2007 ) which does not have restrictions on the number of tolerable faulty nodes and its distribution. However, this algorithm has three crucial problems; (1) this algorithm fails to provide complete and deadlock-free routing, (2) many nonfaulty nodes are contained in faulty blocks and thus deactivated, and (3) complex routing functions are not feasible for hardware implementation. In this paper, we give a solution for each of the above three problems. We correct the errors of Message-Route to make it complete and deadlock-free. Then, we propose a deadlock-free fault-tolerant routing algorithm which can work under small-sized faulty blocks with a simple routing control. Experimental results show that the proposed algorithm significantly reduces the size of faulty blocks and improves communication latency for both random and cluster faults. Moreover, an FPGA implementation of the proposed algorithm is also discussed.</description><subject>Algorithms</subject><subject>CAE) and Design</subject><subject>Circuits and Systems</subject><subject>Clusters</subject><subject>Computer networks</subject><subject>Computer-Aided Engineering (CAD</subject><subject>Electrical Engineering</subject><subject>Electronics</subject><subject>Engineering</subject><subject>Fault tolerance</subject><subject>Faults</subject><subject>Hardware</subject><subject>Integrated circuits</subject><subject>Routing</subject><subject>Routing (telecommunications)</subject><issn>0923-8174</issn><issn>1573-0727</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2013</creationdate><recordtype>article</recordtype><sourceid>ABUWG</sourceid><sourceid>AFKRA</sourceid><sourceid>AZQEC</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><sourceid>GNUQQ</sourceid><recordid>eNp1kEtLAzEURoMoWKs_wF3AjZtoXpPHslSrBR9Q6jqkaWY6dTqpyQzivzdlXIjg6m7O-bgcAC4JviEYy9tEsGICYcJQwaRE-giMSCEZwpLKYzDCmjKkiOSn4CylLc4OLcQILCdw4as6tGhlk1_Dme2bDi1D46NtO7gIfVe3FZw0VYh1t9mVIUJ6B-cx-qpvbITPPm3gi-8-Q3xHeWa6qffn4KS0TfIXP3cM3mb3y-kjenp9mE8nT8hxUnSIOrHSQjqlpSyLQjnN3JqtCeMrKjkvndYlsWvJhbdS2ZJLK4TGtmAlZh5TNgbXw-4-ho_ep87s6uR809jWhz4ZwonUhCmhMnr1B92GPrb5O0OYVphpKkimyEC5GFKKvjT7WO9s_DIEm0NnM3Q2ubM5dDY6O3RwUmbbysdfy_9K31kNfmc</recordid><startdate>20130601</startdate><enddate>20130601</enddate><creator>Fukushima, Yusuke</creator><creator>Fukushi, Masaru</creator><creator>Yairi, Ikuko Eguchi</creator><general>Springer US</general><general>Springer Nature B.V</general><scope>AAYXX</scope><scope>CITATION</scope><scope>3V.</scope><scope>7QF</scope><scope>7QQ</scope><scope>7SC</scope><scope>7SE</scope><scope>7SP</scope><scope>7SR</scope><scope>7TA</scope><scope>7TB</scope><scope>7U5</scope><scope>7XB</scope><scope>88I</scope><scope>88K</scope><scope>8AO</scope><scope>8BQ</scope><scope>8FD</scope><scope>8FE</scope><scope>8FG</scope><scope>8FK</scope><scope>ABJCF</scope><scope>ABUWG</scope><scope>AFKRA</scope><scope>AZQEC</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>F28</scope><scope>FR3</scope><scope>GNUQQ</scope><scope>H8D</scope><scope>H8G</scope><scope>HCIFZ</scope><scope>JG9</scope><scope>JQ2</scope><scope>KR7</scope><scope>L6V</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>M2P</scope><scope>M2T</scope><scope>M7S</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>PRINS</scope><scope>PTHSS</scope><scope>Q9U</scope><scope>S0W</scope></search><sort><creationdate>20130601</creationdate><title>A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip</title><author>Fukushima, Yusuke ; Fukushi, Masaru ; Yairi, Ikuko Eguchi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c415t-2c6b967c8977f558c93cd3d134b2744fc99f1ad746ea78af47a6690a53f03e023</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Algorithms</topic><topic>CAE) and Design</topic><topic>Circuits and Systems</topic><topic>Clusters</topic><topic>Computer networks</topic><topic>Computer-Aided Engineering (CAD</topic><topic>Electrical Engineering</topic><topic>Electronics</topic><topic>Engineering</topic><topic>Fault tolerance</topic><topic>Faults</topic><topic>Hardware</topic><topic>Integrated circuits</topic><topic>Routing</topic><topic>Routing (telecommunications)</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Fukushima, Yusuke</creatorcontrib><creatorcontrib>Fukushi, Masaru</creatorcontrib><creatorcontrib>Yairi, Ikuko Eguchi</creatorcontrib><collection>CrossRef</collection><collection>ProQuest Central (Corporate)</collection><collection>Aluminium Industry Abstracts</collection><collection>Ceramic Abstracts</collection><collection>Computer and Information Systems Abstracts</collection><collection>Corrosion Abstracts</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Engineered Materials Abstracts</collection><collection>Materials Business File</collection><collection>Mechanical &amp; Transportation Engineering Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>ProQuest Central (purchase pre-March 2016)</collection><collection>Science Database (Alumni Edition)</collection><collection>Telecommunications (Alumni Edition)</collection><collection>ProQuest Pharma Collection</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>ProQuest Central (Alumni) (purchase pre-March 2016)</collection><collection>Materials Science &amp; Engineering Collection</collection><collection>ProQuest Central (Alumni Edition)</collection><collection>ProQuest Central UK/Ireland</collection><collection>ProQuest Central Essentials</collection><collection>ProQuest Central</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central Korea</collection><collection>ANTE: Abstracts in New Technology &amp; Engineering</collection><collection>Engineering Research Database</collection><collection>ProQuest Central Student</collection><collection>Aerospace Database</collection><collection>Copper Technical Reference Library</collection><collection>SciTech Premium Collection</collection><collection>Materials Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Civil Engineering Abstracts</collection><collection>ProQuest Engineering Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Science Database</collection><collection>Telecommunications Database</collection><collection>Engineering Database</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>ProQuest Central China</collection><collection>Engineering Collection</collection><collection>ProQuest Central Basic</collection><collection>DELNET Engineering &amp; Technology Collection</collection><jtitle>Journal of electronic testing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Fukushima, Yusuke</au><au>Fukushi, Masaru</au><au>Yairi, Ikuko Eguchi</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip</atitle><jtitle>Journal of electronic testing</jtitle><stitle>J Electron Test</stitle><date>2013-06-01</date><risdate>2013</risdate><volume>29</volume><issue>3</issue><spage>415</spage><epage>429</epage><pages>415-429</pages><issn>0923-8174</issn><eissn>1573-0727</eissn><abstract>This paper presents a deadlock-free fault-tolerant routing algorithm for irregular mesh network-on-chips based on a region-based approach. In this approach, a set of rectangular faulty regions called faulty blocks is formed for faulty nodes and a detour path is defined for each faulty block to indicate how packets must detour thefaulty block. The most recent routing algorithm on this approach is Message-Route (Holsmark and Kumar J Inf Sci Eng 23:1649–1662, 2007 ) which does not have restrictions on the number of tolerable faulty nodes and its distribution. However, this algorithm has three crucial problems; (1) this algorithm fails to provide complete and deadlock-free routing, (2) many nonfaulty nodes are contained in faulty blocks and thus deactivated, and (3) complex routing functions are not feasible for hardware implementation. In this paper, we give a solution for each of the above three problems. We correct the errors of Message-Route to make it complete and deadlock-free. Then, we propose a deadlock-free fault-tolerant routing algorithm which can work under small-sized faulty blocks with a simple routing control. Experimental results show that the proposed algorithm significantly reduces the size of faulty blocks and improves communication latency for both random and cluster faults. Moreover, an FPGA implementation of the proposed algorithm is also discussed.</abstract><cop>Boston</cop><pub>Springer US</pub><doi>10.1007/s10836-013-5377-9</doi><tpages>15</tpages></addata></record>
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1573-0727
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subjects Algorithms
CAE) and Design
Circuits and Systems
Clusters
Computer networks
Computer-Aided Engineering (CAD
Electrical Engineering
Electronics
Engineering
Fault tolerance
Faults
Hardware
Integrated circuits
Routing
Routing (telecommunications)
title A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T23%3A55%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20Region-based%20Fault-Tolerant%20Routing%20Algorithmfor%202D%20Irregular%20Mesh%20Network-on-Chip&rft.jtitle=Journal%20of%20electronic%20testing&rft.au=Fukushima,%20Yusuke&rft.date=2013-06-01&rft.volume=29&rft.issue=3&rft.spage=415&rft.epage=429&rft.pages=415-429&rft.issn=0923-8174&rft.eissn=1573-0727&rft_id=info:doi/10.1007/s10836-013-5377-9&rft_dat=%3Cproquest_cross%3E3012976181%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1398039261&rft_id=info:pmid/&rfr_iscdi=true