A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip
This paper presents a deadlock-free fault-tolerant routing algorithm for irregular mesh network-on-chips based on a region-based approach. In this approach, a set of rectangular faulty regions called faulty blocks is formed for faulty nodes and a detour path is defined for each faulty block to indic...
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Veröffentlicht in: | Journal of electronic testing 2013-06, Vol.29 (3), p.415-429 |
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description | This paper presents a deadlock-free fault-tolerant routing algorithm for irregular mesh network-on-chips based on a region-based approach. In this approach, a set of rectangular faulty regions called faulty blocks is formed for faulty nodes and a detour path is defined for each faulty block to indicate how packets must detour thefaulty block. The most recent routing algorithm on this approach is Message-Route (Holsmark and Kumar J Inf Sci Eng 23:1649–1662,
2007
) which does not have restrictions on the number of tolerable faulty nodes and its distribution. However, this algorithm has three crucial problems; (1) this algorithm fails to provide complete and deadlock-free routing, (2) many nonfaulty nodes are contained in faulty blocks and thus deactivated, and (3) complex routing functions are not feasible for hardware implementation. In this paper, we give a solution for each of the above three problems. We correct the errors of Message-Route to make it complete and deadlock-free. Then, we propose a deadlock-free fault-tolerant routing algorithm which can work under small-sized faulty blocks with a simple routing control. Experimental results show that the proposed algorithm significantly reduces the size of faulty blocks and improves communication latency for both random and cluster faults. Moreover, an FPGA implementation of the proposed algorithm is also discussed. |
doi_str_mv | 10.1007/s10836-013-5377-9 |
format | Article |
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2007
) which does not have restrictions on the number of tolerable faulty nodes and its distribution. However, this algorithm has three crucial problems; (1) this algorithm fails to provide complete and deadlock-free routing, (2) many nonfaulty nodes are contained in faulty blocks and thus deactivated, and (3) complex routing functions are not feasible for hardware implementation. In this paper, we give a solution for each of the above three problems. We correct the errors of Message-Route to make it complete and deadlock-free. Then, we propose a deadlock-free fault-tolerant routing algorithm which can work under small-sized faulty blocks with a simple routing control. Experimental results show that the proposed algorithm significantly reduces the size of faulty blocks and improves communication latency for both random and cluster faults. Moreover, an FPGA implementation of the proposed algorithm is also discussed.</description><identifier>ISSN: 0923-8174</identifier><identifier>EISSN: 1573-0727</identifier><identifier>DOI: 10.1007/s10836-013-5377-9</identifier><language>eng</language><publisher>Boston: Springer US</publisher><subject>Algorithms ; CAE) and Design ; Circuits and Systems ; Clusters ; Computer networks ; Computer-Aided Engineering (CAD ; Electrical Engineering ; Electronics ; Engineering ; Fault tolerance ; Faults ; Hardware ; Integrated circuits ; Routing ; Routing (telecommunications)</subject><ispartof>Journal of electronic testing, 2013-06, Vol.29 (3), p.415-429</ispartof><rights>Springer Science+Business Media New York 2013</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c415t-2c6b967c8977f558c93cd3d134b2744fc99f1ad746ea78af47a6690a53f03e023</citedby><cites>FETCH-LOGICAL-c415t-2c6b967c8977f558c93cd3d134b2744fc99f1ad746ea78af47a6690a53f03e023</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/s10836-013-5377-9$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://link.springer.com/10.1007/s10836-013-5377-9$$EHTML$$P50$$Gspringer$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,41488,42557,51319</link.rule.ids></links><search><creatorcontrib>Fukushima, Yusuke</creatorcontrib><creatorcontrib>Fukushi, Masaru</creatorcontrib><creatorcontrib>Yairi, Ikuko Eguchi</creatorcontrib><title>A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip</title><title>Journal of electronic testing</title><addtitle>J Electron Test</addtitle><description>This paper presents a deadlock-free fault-tolerant routing algorithm for irregular mesh network-on-chips based on a region-based approach. In this approach, a set of rectangular faulty regions called faulty blocks is formed for faulty nodes and a detour path is defined for each faulty block to indicate how packets must detour thefaulty block. The most recent routing algorithm on this approach is Message-Route (Holsmark and Kumar J Inf Sci Eng 23:1649–1662,
2007
) which does not have restrictions on the number of tolerable faulty nodes and its distribution. However, this algorithm has three crucial problems; (1) this algorithm fails to provide complete and deadlock-free routing, (2) many nonfaulty nodes are contained in faulty blocks and thus deactivated, and (3) complex routing functions are not feasible for hardware implementation. In this paper, we give a solution for each of the above three problems. We correct the errors of Message-Route to make it complete and deadlock-free. Then, we propose a deadlock-free fault-tolerant routing algorithm which can work under small-sized faulty blocks with a simple routing control. Experimental results show that the proposed algorithm significantly reduces the size of faulty blocks and improves communication latency for both random and cluster faults. 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In this approach, a set of rectangular faulty regions called faulty blocks is formed for faulty nodes and a detour path is defined for each faulty block to indicate how packets must detour thefaulty block. The most recent routing algorithm on this approach is Message-Route (Holsmark and Kumar J Inf Sci Eng 23:1649–1662,
2007
) which does not have restrictions on the number of tolerable faulty nodes and its distribution. However, this algorithm has three crucial problems; (1) this algorithm fails to provide complete and deadlock-free routing, (2) many nonfaulty nodes are contained in faulty blocks and thus deactivated, and (3) complex routing functions are not feasible for hardware implementation. In this paper, we give a solution for each of the above three problems. We correct the errors of Message-Route to make it complete and deadlock-free. Then, we propose a deadlock-free fault-tolerant routing algorithm which can work under small-sized faulty blocks with a simple routing control. Experimental results show that the proposed algorithm significantly reduces the size of faulty blocks and improves communication latency for both random and cluster faults. Moreover, an FPGA implementation of the proposed algorithm is also discussed.</abstract><cop>Boston</cop><pub>Springer US</pub><doi>10.1007/s10836-013-5377-9</doi><tpages>15</tpages></addata></record> |
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subjects | Algorithms CAE) and Design Circuits and Systems Clusters Computer networks Computer-Aided Engineering (CAD Electrical Engineering Electronics Engineering Fault tolerance Faults Hardware Integrated circuits Routing Routing (telecommunications) |
title | A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip |
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