Software-defined DVT-T2 demodulator using scalable DSP processors

This paper describes the feasibility of software-defined demodulator of DVB-T2 standard using the scalable DSP processor. This paper focuses mainly on the DVB-T2 receiver design and implementation of four major software blocks of the demodulator: FFTs, channel estimator, multi-level de-interleavers...

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Veröffentlicht in:	IEEE transactions on consumer electronics 2013-05, Vol.59 (2), p.428-434
Hauptverfasser:	Ho Yang, Basutkar, N., Peng Xue, Kyeongyeon Kim, Young-Hwan Park
Format:	Artikel
Sprache:	eng
Schlagworte:	CGRA processor Channel estimation Computer architecture Computer programs Decoding Demodulation Demodulators Digital signal processing Digital video broadcasting DVB-T2 Electronics Mathematical analysis Mathematical models Processors Program processors Software software-defined demodulator softwaredefinedradio
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