Domino logic designs for high-performance and leakage-tolerant applications
Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose several domino logic circuit techniques to improve the robustness and performance along with leakage power. Lower total power consumption is achieved by utili...
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| Veröffentlicht in: | Integration (Amsterdam) 2013-06, Vol.46 (3), p.247-254 |
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| container_title | Integration (Amsterdam) |
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| creator | Moradi, Farshad Vu Cao, Tuan Vatajelu, Elena I. Peiravi, Ali Mahmoodi, Hamid Wisland, Dag T. |
| description | Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose several domino logic circuit techniques to improve the robustness and performance along with leakage power. Lower total power consumption is achieved by utilizing proposed techniques. According to the simulations in TSMC 65nm CMOS process, the proposed circuits increase noise immunity for wide OR gates by at least 3.5X and shows performance improvement of up to 20% compared to conventional domino logic circuits. For FinFET simulation TCAD tools have been used.
► New domino logic circuits using CMOS 65nm technology are proposed and simulated. ► A domino logic circuit using FinFET is presented and simulated using TCAD tools. ► The proposed circuits increase noise immunity by at least 3.5X. ► Proposed designs improve performance compared to conventional domino logic design. |
| doi_str_mv | 10.1016/j.vlsi.2012.04.005 |
| format | Article |
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► New domino logic circuits using CMOS 65nm technology are proposed and simulated. ► A domino logic circuit using FinFET is presented and simulated using TCAD tools. ► The proposed circuits increase noise immunity by at least 3.5X. ► Proposed designs improve performance compared to conventional domino logic design.</description><identifier>ISSN: 0167-9260</identifier><identifier>EISSN: 1872-7522</identifier><identifier>DOI: 10.1016/j.vlsi.2012.04.005</identifier><identifier>CODEN: IVJODL</identifier><language>eng</language><publisher>Amsterdam: Elsevier B.V</publisher><subject>Applied sciences ; Circuit properties ; Circuits ; CMOS ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; Domino logic ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; FinFET ; High-speed ; Integrated circuits ; Leakage ; Logic circuits ; Logic design ; Power consumption ; Robustness ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Simulation ; Transistors</subject><ispartof>Integration (Amsterdam), 2013-06, Vol.46 (3), p.247-254</ispartof><rights>2012 Elsevier B.V.</rights><rights>2014 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c363t-246d18633af36de6d9f69c2be8eab3d68727d7befb8455f462aabcd15532f0563</citedby><cites>FETCH-LOGICAL-c363t-246d18633af36de6d9f69c2be8eab3d68727d7befb8455f462aabcd15532f0563</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://www.sciencedirect.com/science/article/pii/S0167926012000338$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>314,776,780,3536,27903,27904,65309</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=27402214$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Moradi, Farshad</creatorcontrib><creatorcontrib>Vu Cao, Tuan</creatorcontrib><creatorcontrib>Vatajelu, Elena I.</creatorcontrib><creatorcontrib>Peiravi, Ali</creatorcontrib><creatorcontrib>Mahmoodi, Hamid</creatorcontrib><creatorcontrib>Wisland, Dag T.</creatorcontrib><title>Domino logic designs for high-performance and leakage-tolerant applications</title><title>Integration (Amsterdam)</title><description>Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose several domino logic circuit techniques to improve the robustness and performance along with leakage power. Lower total power consumption is achieved by utilizing proposed techniques. According to the simulations in TSMC 65nm CMOS process, the proposed circuits increase noise immunity for wide OR gates by at least 3.5X and shows performance improvement of up to 20% compared to conventional domino logic circuits. For FinFET simulation TCAD tools have been used.
► New domino logic circuits using CMOS 65nm technology are proposed and simulated. ► A domino logic circuit using FinFET is presented and simulated using TCAD tools. ► The proposed circuits increase noise immunity by at least 3.5X. ► Proposed designs improve performance compared to conventional domino logic design.</description><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>Circuits</subject><subject>CMOS</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Domino logic</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>FinFET</subject><subject>High-speed</subject><subject>Integrated circuits</subject><subject>Leakage</subject><subject>Logic circuits</subject><subject>Logic design</subject><subject>Power consumption</subject><subject>Robustness</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Technologies. Operation analysis. Testing</topic><topic>Digital circuits</topic><topic>Domino logic</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>FinFET</topic><topic>High-speed</topic><topic>Integrated circuits</topic><topic>Leakage</topic><topic>Logic circuits</topic><topic>Logic design</topic><topic>Power consumption</topic><topic>Robustness</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Simulation</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Moradi, Farshad</creatorcontrib><creatorcontrib>Vu Cao, Tuan</creatorcontrib><creatorcontrib>Vatajelu, Elena I.</creatorcontrib><creatorcontrib>Peiravi, Ali</creatorcontrib><creatorcontrib>Mahmoodi, Hamid</creatorcontrib><creatorcontrib>Wisland, Dag T.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Integration (Amsterdam)</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Moradi, Farshad</au><au>Vu Cao, Tuan</au><au>Vatajelu, Elena I.</au><au>Peiravi, Ali</au><au>Mahmoodi, Hamid</au><au>Wisland, Dag T.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Domino logic designs for high-performance and leakage-tolerant applications</atitle><jtitle>Integration (Amsterdam)</jtitle><date>2013-06-01</date><risdate>2013</risdate><volume>46</volume><issue>3</issue><spage>247</spage><epage>254</epage><pages>247-254</pages><issn>0167-9260</issn><eissn>1872-7522</eissn><coden>IVJODL</coden><abstract>Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose several domino logic circuit techniques to improve the robustness and performance along with leakage power. Lower total power consumption is achieved by utilizing proposed techniques. According to the simulations in TSMC 65nm CMOS process, the proposed circuits increase noise immunity for wide OR gates by at least 3.5X and shows performance improvement of up to 20% compared to conventional domino logic circuits. For FinFET simulation TCAD tools have been used.
► New domino logic circuits using CMOS 65nm technology are proposed and simulated. ► A domino logic circuit using FinFET is presented and simulated using TCAD tools. ► The proposed circuits increase noise immunity by at least 3.5X. ► Proposed designs improve performance compared to conventional domino logic design.</abstract><cop>Amsterdam</cop><pub>Elsevier B.V</pub><doi>10.1016/j.vlsi.2012.04.005</doi><tpages>8</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0167-9260 |
| ispartof | Integration (Amsterdam), 2013-06, Vol.46 (3), p.247-254 |
| issn | 0167-9260 1872-7522 |
| language | eng |
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| source | Elsevier ScienceDirect Journals |
| subjects | Applied sciences Circuit properties Circuits CMOS Design. Technologies. Operation analysis. Testing Digital circuits Domino logic Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology FinFET High-speed Integrated circuits Leakage Logic circuits Logic design Power consumption Robustness Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Simulation Transistors |
| title | Domino logic designs for high-performance and leakage-tolerant applications |
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