A column parity based fault detection mechanism for FIFO buffers

This paper presents a low cost fault detection mechanism for FIFO buffers. The scheme is based on column parity maintenance in a single register, which is updated by monitoring the values written to and read from the FIFO memory array. A non-zero column parity when the FIFO is empty, constitutes an indication of fault, and this property is exploited for fault detection. The technique has gains in area, power and critical path delay, at the expense of (1) greater detection latency, due to the need for the FIFO to become empty in order to assert a violation and (2) worse Silent Data Corruption (SDC) rate. ► A low cost fault detection mechanism for FIFO buffers is presented. ► It has low critical path, area and power overheads. ► But it has greater detection latency and Silent Data Corruption rate. ► The fault coverage of the mechanism is analytically estimated. ► Detection latency results are shown for some case studies.