A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder
The H.264/AVC video coding standard can deliver high compression efficiency at a cost of increased complexity and power. The increasing popularity of video capture and playback on portable devices requires that the power of the video codec be kept to a minimum. This work implements several architect...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2009-11, Vol.44 (11), p.2943-2956 |
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| container_issue | 11 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 44 |
| creator | Sze, V. Finchelstein, D.F. Sinangil, M.E. Chandrakasan, A.P. |
| description | The H.264/AVC video coding standard can deliver high compression efficiency at a cost of increased complexity and power. The increasing popularity of video capture and playback on portable devices requires that the power of the video codec be kept to a minimum. This work implements several architecture optimizations such as increased parallelism, pipelining with FIFOs, multiple voltage/frequency domains, and custom voltage-scalable SRAMs that enable low voltage operation to reduce the power of a high-definition decoder. Dynamic voltage and frequency scaling can efficiently adapt to the varying workloads by leveraging the low voltage capabilities and domain partitioning of the decoder. An H.264/AVC Baseline Level 3.2 decoder ASIC was fabricated in 65-nm CMOS and verified. For high definition 720p video decoding at 30 frames per second (fps), it operates down to 0.7 V with a measured power of 1.8 mW, which is significantly lower than previously published results. The highly scalable decoder is capable of operating down to 0.5 V for decoding QCIF at 15 fps with a measured power of 29 muW. |
| doi_str_mv | 10.1109/JSSC.2009.2028933 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_1365156756</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5308724</ieee_id><sourcerecordid>2567655161</sourcerecordid><originalsourceid>FETCH-LOGICAL-c462t-339f19d3600e8774a52276c7e589d9b42bac36efd9ebf576bfe21dab34eb3d33</originalsourceid><addsrcrecordid>eNqN0ctKw0AUBuBBFKyXBxA3QVAESTpzzlyXpV6qFFy0VHfDJDmBlLapGbvw7U1pceFC3MwwzHd-OPyMXQieCcFd_2UyGWbAuesOsA7xgPWEUjYVBt8PWY9zYVPXgWN2EuO8e0ppRY_dDRKemXSWiMymy7dklIGW_cFsmBjg62RWl9Qk91Q0JbVn7KgKi0jn-_uUTR8fpsNROn59eh4OxmkhNXymiK4SrkTNOVljZFAARheGlHWlyyXkoUBNVekor5TReUUgypCjpBxLxFN2s4tdt83HhuKnX9axoMUirKjZRI8anOOCd_D2TyhQK6G0Ufp_FCVa6OjVLzpvNu2qW9g7YQCcdds8sUNF28TYUuXXbb0M7ZcX3G8L8dtC_LYQvy-km7neB4dYhEXVhlVRx59BAOlAc9O5y52riejnWyG3BiR-A9EWjIQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>917229896</pqid></control><display><type>article</type><title>A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder</title><source>IEEE Electronic Library (IEL)</source><creator>Sze, V. ; Finchelstein, D.F. ; Sinangil, M.E. ; Chandrakasan, A.P.</creator><creatorcontrib>Sze, V. ; Finchelstein, D.F. ; Sinangil, M.E. ; Chandrakasan, A.P.</creatorcontrib><description>The H.264/AVC video coding standard can deliver high compression efficiency at a cost of increased complexity and power. The increasing popularity of video capture and playback on portable devices requires that the power of the video codec be kept to a minimum. This work implements several architecture optimizations such as increased parallelism, pipelining with FIFOs, multiple voltage/frequency domains, and custom voltage-scalable SRAMs that enable low voltage operation to reduce the power of a high-definition decoder. Dynamic voltage and frequency scaling can efficiently adapt to the varying workloads by leveraging the low voltage capabilities and domain partitioning of the decoder. An H.264/AVC Baseline Level 3.2 decoder ASIC was fabricated in 65-nm CMOS and verified. For high definition 720p video decoding at 30 frames per second (fps), it operates down to 0.7 V with a measured power of 1.8 mW, which is significantly lower than previously published results. The highly scalable decoder is capable of operating down to 0.5 V for decoding QCIF at 15 fps with a measured power of 29 muW.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2009.2028933</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Automatic voltage control ; cache memories ; Circuit properties ; CMOS digital integrated circuits ; CMOS memory circuits ; Coding standards ; Costs ; Decoders ; Decoding ; Design. Technologies. Operation analysis. Testing ; Devices ; Dynamic voltage scaling ; Electric potential ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; H.264/AVC ; High definition ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Low voltage ; low-power electronics ; Partitioning ; Pipeline processing ; Power measurement ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Signal convertors ; SRAM chips ; Video codecs ; Video coding ; Video compression ; Voltage</subject><ispartof>IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.2943-2956</ispartof><rights>2015 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2009</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c462t-339f19d3600e8774a52276c7e589d9b42bac36efd9ebf576bfe21dab34eb3d33</citedby><cites>FETCH-LOGICAL-c462t-339f19d3600e8774a52276c7e589d9b42bac36efd9ebf576bfe21dab34eb3d33</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5308724$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,776,780,785,786,792,23909,23910,25118,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5308724$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=22492607$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Sze, V.</creatorcontrib><creatorcontrib>Finchelstein, D.F.</creatorcontrib><creatorcontrib>Sinangil, M.E.</creatorcontrib><creatorcontrib>Chandrakasan, A.P.</creatorcontrib><title>A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>The H.264/AVC video coding standard can deliver high compression efficiency at a cost of increased complexity and power. The increasing popularity of video capture and playback on portable devices requires that the power of the video codec be kept to a minimum. This work implements several architecture optimizations such as increased parallelism, pipelining with FIFOs, multiple voltage/frequency domains, and custom voltage-scalable SRAMs that enable low voltage operation to reduce the power of a high-definition decoder. Dynamic voltage and frequency scaling can efficiently adapt to the varying workloads by leveraging the low voltage capabilities and domain partitioning of the decoder. An H.264/AVC Baseline Level 3.2 decoder ASIC was fabricated in 65-nm CMOS and verified. For high definition 720p video decoding at 30 frames per second (fps), it operates down to 0.7 V with a measured power of 1.8 mW, which is significantly lower than previously published results. The highly scalable decoder is capable of operating down to 0.5 V for decoding QCIF at 15 fps with a measured power of 29 muW.</description><subject>Applied sciences</subject><subject>Automatic voltage control</subject><subject>cache memories</subject><subject>Circuit properties</subject><subject>CMOS digital integrated circuits</subject><subject>CMOS memory circuits</subject><subject>Coding standards</subject><subject>Costs</subject><subject>Decoders</subject><subject>Decoding</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Devices</subject><subject>Dynamic voltage scaling</subject><subject>Electric potential</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>H.264/AVC</subject><subject>High definition</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Low voltage</subject><subject>low-power electronics</subject><subject>Partitioning</subject><subject>Pipeline processing</subject><subject>Power measurement</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Signal convertors</subject><subject>SRAM chips</subject><subject>Video codecs</subject><subject>Video coding</subject><subject>Video compression</subject><subject>Voltage</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2009</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqN0ctKw0AUBuBBFKyXBxA3QVAESTpzzlyXpV6qFFy0VHfDJDmBlLapGbvw7U1pceFC3MwwzHd-OPyMXQieCcFd_2UyGWbAuesOsA7xgPWEUjYVBt8PWY9zYVPXgWN2EuO8e0ppRY_dDRKemXSWiMymy7dklIGW_cFsmBjg62RWl9Qk91Q0JbVn7KgKi0jn-_uUTR8fpsNROn59eh4OxmkhNXymiK4SrkTNOVljZFAARheGlHWlyyXkoUBNVekor5TReUUgypCjpBxLxFN2s4tdt83HhuKnX9axoMUirKjZRI8anOOCd_D2TyhQK6G0Ufp_FCVa6OjVLzpvNu2qW9g7YQCcdds8sUNF28TYUuXXbb0M7ZcX3G8L8dtC_LYQvy-km7neB4dYhEXVhlVRx59BAOlAc9O5y52riejnWyG3BiR-A9EWjIQ</recordid><startdate>20091101</startdate><enddate>20091101</enddate><creator>Sze, V.</creator><creator>Finchelstein, D.F.</creator><creator>Sinangil, M.E.</creator><creator>Chandrakasan, A.P.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20091101</creationdate><title>A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder</title><author>Sze, V. ; Finchelstein, D.F. ; Sinangil, M.E. ; Chandrakasan, A.P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c462t-339f19d3600e8774a52276c7e589d9b42bac36efd9ebf576bfe21dab34eb3d33</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Applied sciences</topic><topic>Automatic voltage control</topic><topic>cache memories</topic><topic>Circuit properties</topic><topic>CMOS digital integrated circuits</topic><topic>CMOS memory circuits</topic><topic>Coding standards</topic><topic>Costs</topic><topic>Decoders</topic><topic>Decoding</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Devices</topic><topic>Dynamic voltage scaling</topic><topic>Electric potential</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>H.264/AVC</topic><topic>High definition</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Low voltage</topic><topic>low-power electronics</topic><topic>Partitioning</topic><topic>Pipeline processing</topic><topic>Power measurement</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Signal convertors</topic><topic>SRAM chips</topic><topic>Video codecs</topic><topic>Video coding</topic><topic>Video compression</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Sze, V.</creatorcontrib><creatorcontrib>Finchelstein, D.F.</creatorcontrib><creatorcontrib>Sinangil, M.E.</creatorcontrib><creatorcontrib>Chandrakasan, A.P.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sze, V.</au><au>Finchelstein, D.F.</au><au>Sinangil, M.E.</au><au>Chandrakasan, A.P.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2009-11-01</date><risdate>2009</risdate><volume>44</volume><issue>11</issue><spage>2943</spage><epage>2956</epage><pages>2943-2956</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>The H.264/AVC video coding standard can deliver high compression efficiency at a cost of increased complexity and power. The increasing popularity of video capture and playback on portable devices requires that the power of the video codec be kept to a minimum. This work implements several architecture optimizations such as increased parallelism, pipelining with FIFOs, multiple voltage/frequency domains, and custom voltage-scalable SRAMs that enable low voltage operation to reduce the power of a high-definition decoder. Dynamic voltage and frequency scaling can efficiently adapt to the varying workloads by leveraging the low voltage capabilities and domain partitioning of the decoder. An H.264/AVC Baseline Level 3.2 decoder ASIC was fabricated in 65-nm CMOS and verified. For high definition 720p video decoding at 30 frames per second (fps), it operates down to 0.7 V with a measured power of 1.8 mW, which is significantly lower than previously published results. The highly scalable decoder is capable of operating down to 0.5 V for decoding QCIF at 15 fps with a measured power of 29 muW.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2009.2028933</doi><tpages>14</tpages><oa>free_for_read</oa></addata></record> |
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| ispartof | IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.2943-2956 |
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| subjects | Applied sciences Automatic voltage control cache memories Circuit properties CMOS digital integrated circuits CMOS memory circuits Coding standards Costs Decoders Decoding Design. Technologies. Operation analysis. Testing Devices Dynamic voltage scaling Electric potential Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology H.264/AVC High definition Integrated circuits Integrated circuits by function (including memories and processors) Low voltage low-power electronics Partitioning Pipeline processing Power measurement Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors SRAM chips Video codecs Video coding Video compression Voltage |
| title | A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-12T17%3A09%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%200.7-V%201.8-mW%20H.264/AVC%20720p%20Video%20Decoder&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Sze,%20V.&rft.date=2009-11-01&rft.volume=44&rft.issue=11&rft.spage=2943&rft.epage=2956&rft.pages=2943-2956&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2009.2028933&rft_dat=%3Cproquest_RIE%3E2567655161%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=917229896&rft_id=info:pmid/&rft_ieee_id=5308724&rfr_iscdi=true |