Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation

For nanoscale CMOS devices, gate roughness has severe impact on the device I - V characteristics, particularly in the subthreshold region. In particular, the nonrectangular gate (NRG) geometries are caused by subwavelength lithography and have relatively low spatial frequency. In this paper, we pres...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2010-04, Vol.18 (4), p.666-670
Hauptverfasser:	Singal, R., Balijepalli, A., Subramaniam, A., Chi-Chao Wang, Liu, F., Nassif, S.R., Yu Cao
Format:	Artikel
Sprache:	eng
Schlagworte:	Analytical models Bias Circuit simulation Computer simulation Devices Electric potential Equivalent gate length (EGL) Frequency Gates (circuits) Geometry Integrated circuit technology leakage line-edge roughness (LER) Lithography Mathematical models Nanoscale devices Nanostructure narrow-width effect (NWE) nonrectangular gate (NRG) Predictive models Semiconductor device modeling Studies Very large scale integration Voltage
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