Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation

For nanoscale CMOS devices, gate roughness has severe impact on the device I - V characteristics, particularly in the subthreshold region. In particular, the nonrectangular gate (NRG) geometries are caused by subwavelength lithography and have relatively low spatial frequency. In this paper, we present an analytical approach to model NRG effects on I - V characteristics. To predict the change of I - V characteristics due to the NRG effect, the proposed model converts the postlithography gate profile into an equivalent gate length ( Le ) , which is a function of the gate bias voltage but independent of the drain bias voltage. We demonstrate the accuracy of this approach by comparing it to TCAD simulation results for 65-nm technology. The new Le model is readily integrated into standard transistor models in traditional circuit simulation tools, such as SPICE, for both dc and transient analyses. We further develop a generic procedure to systematically extract the Le value from the postlithography gate profile. The interaction with the narrow-width effect is also efficiently incorporated into the proposed algorithm. TCAD verification demonstrates that the proposed Le model is simple for implementation, scalable with both transistor geometries and bias conditions, and also continuous across all the operation regions.