On an Improved FPGA Implementation of CNN-Based Gabor-Type Filters
In this brief, the details of the architecture of a previously introduced improved field-programmable gate array implementation of the cellular neural network (CNN)-based 2-D Gabor-type filter are given, and the implementation results are discussed. The proposed architecture is suitable for real-tim...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2012-11, Vol.59 (11), p.815-819 |
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| container_title | IEEE transactions on circuits and systems. II, Express briefs |
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| creator | Cesur, E. Yildiz, N. Tavsanoglu, V. |
| description | In this brief, the details of the architecture of a previously introduced improved field-programmable gate array implementation of the cellular neural network (CNN)-based 2-D Gabor-type filter are given, and the implementation results are discussed. The proposed architecture is suitable for real-time applications with high pixel rates. The prototype is capable of processing video streams up to a pixel rate of 373.2 megapixels per second (MP/s), including full-high-definition (HD) 1080p@60 (1080 × 1920 resolution, 60-Hz frame rate, and 124.4-MP/s visible pixel rate). This brief also contains convergence rate analysis results, along with some discussions on FIR and CNN-based implementation methods. |
| doi_str_mv | 10.1109/TCSII.2012.2218471 |
| format | Article |
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The proposed architecture is suitable for real-time applications with high pixel rates. The prototype is capable of processing video streams up to a pixel rate of 373.2 megapixels per second (MP/s), including full-high-definition (HD) 1080p@60 (1080 × 1920 resolution, 60-Hz frame rate, and 124.4-MP/s visible pixel rate). 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This brief also contains convergence rate analysis results, along with some discussions on FIR and CNN-based implementation methods.</description><subject>Architecture</subject><subject>Bandwidth</subject><subject>Cellular neural networks (CNNs)</subject><subject>Circuits</subject><subject>Computer architecture</subject><subject>Convergence</subject><subject>Equations</subject><subject>Field programmable gate arrays</subject><subject>field-programmable gate arrays (FPGAs)</subject><subject>Finite impulse response filter</subject><subject>Gabor filters</subject><subject>Neural networks</subject><subject>Pixels</subject><subject>Real time</subject><subject>real-time systems</subject><subject>reconfigurable architectures</subject><subject>Streams</subject><issn>1549-7747</issn><issn>1558-3791</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2012</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkEFLwzAUx4MoOKdfQC8FL14685ImaY5bcbMwNsHeQ5q-QkfXzqYT9u1t3fDgKS-83__x50fII9AZANWvWfKZpjNGgc0YgzhScEUmIEQccqXhepwjHSoVqVty5_2OUqYpZxOy2DaBbYJ0f-jabyyC5cdqPv5q3GPT275qm6Atg2SzCRfWD8DK5m0XZqcDBsuq7rHz9-SmtLXHh8s7JdnyLUvew_V2lSbzdeg4i_swj0qpcpBYSC2ojZ2OSircsCyBO62YLIQuMJeldSJ3uRBCI4uAC2alUHxKXs5nh6ZfR_S92VfeYV3bBtujN8BBSCG10gP6_A_dtceuGcoZYDKmWko5UuxMua71vsPSHLpqb7uTAWpGq-bXqhmtmovVIfR0DlWI-BeQPAI6dPwBjylwxQ</recordid><startdate>20121101</startdate><enddate>20121101</enddate><creator>Cesur, E.</creator><creator>Yildiz, N.</creator><creator>Tavsanoglu, V.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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II, Express briefs</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Cesur, E.</au><au>Yildiz, N.</au><au>Tavsanoglu, V.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>On an Improved FPGA Implementation of CNN-Based Gabor-Type Filters</atitle><jtitle>IEEE transactions on circuits and systems. II, Express briefs</jtitle><stitle>TCSII</stitle><date>2012-11-01</date><risdate>2012</risdate><volume>59</volume><issue>11</issue><spage>815</spage><epage>819</epage><pages>815-819</pages><issn>1549-7747</issn><eissn>1558-3791</eissn><coden>ICSPE5</coden><abstract>In this brief, the details of the architecture of a previously introduced improved field-programmable gate array implementation of the cellular neural network (CNN)-based 2-D Gabor-type filter are given, and the implementation results are discussed. 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| identifier | ISSN: 1549-7747 |
| ispartof | IEEE transactions on circuits and systems. II, Express briefs, 2012-11, Vol.59 (11), p.815-819 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Architecture Bandwidth Cellular neural networks (CNNs) Circuits Computer architecture Convergence Equations Field programmable gate arrays field-programmable gate arrays (FPGAs) Finite impulse response filter Gabor filters Neural networks Pixels Real time real-time systems reconfigurable architectures Streams |
| title | On an Improved FPGA Implementation of CNN-Based Gabor-Type Filters |
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