A Multi-Gigabit Parallel Demodulator and Its FPGA Implementation
This letter presents the architecture of multi-gigabit parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform. The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel...
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| Veröffentlicht in: | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Communications and Computer Sciences, 2012/08/01, Vol.E95.A(8), pp.1412-1415 |
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| container_title | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
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| creator | LIN, Changxing ZHANG, Jian SHAO, Beibei |
| description | This letter presents the architecture of multi-gigabit parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform. The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel FIFO based delete-keep algorithm is proposed for timing synchronization, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier synchronization. A fully pipelined parallel adaptive blind equalization algorithm is also proposed. Their parallel implementation structures suitable for FPGA platform are investigated. Besides, in the demonstration of 2Gbps demodulator for 16QAM modulation, the architecture is implemented and validated on a Xilinx V6 FPGA platform with performance loss less than 2dB. |
| doi_str_mv | 10.1587/transfun.E95.A.1412 |
| format | Article |
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The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel FIFO based delete-keep algorithm is proposed for timing synchronization, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier synchronization. A fully pipelined parallel adaptive blind equalization algorithm is also proposed. Their parallel implementation structures suitable for FPGA platform are investigated. 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Fundamentals</addtitle><date>2012</date><risdate>2012</risdate><volume>E95.A</volume><issue>8</issue><spage>1412</spage><epage>1415</epage><pages>1412-1415</pages><issn>0916-8508</issn><eissn>1745-1337</eissn><abstract>This letter presents the architecture of multi-gigabit parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform. The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel FIFO based delete-keep algorithm is proposed for timing synchronization, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier synchronization. A fully pipelined parallel adaptive blind equalization algorithm is also proposed. Their parallel implementation structures suitable for FPGA platform are investigated. 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| ispartof | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2012/08/01, Vol.E95.A(8), pp.1412-1415 |
| issn | 0916-8508 1745-1337 |
| language | eng |
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| subjects | Algorithms Architecture Demodulators Field programmable gate arrays FPGA implementation frequency domain arithmetic parallel adaptive blind equalization parallel demodulation parallel synchronization Platforms Synchronism Synchronization Time measurements |
| title | A Multi-Gigabit Parallel Demodulator and Its FPGA Implementation |
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