Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors
Global Signal Vulnerability (GSV) analysis is a novel method for assessing the susceptibility of modern microprocessor state elements to failures in the field of operation. In order to effectively allocate design for reliability resources, GSV analysis takes into account the high degree of architect...
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description | Global Signal Vulnerability (GSV) analysis is a novel method for assessing the susceptibility of modern microprocessor state elements to failures in the field of operation. In order to effectively allocate design for reliability resources, GSV analysis takes into account the high degree of architectural masking exhibited in modern microprocessors and ranks state elements accordingly. The novelty of this method lies in the way this ranking is computed. GSV analysis operates either at the Register Transfer (RT-) or at the Gate-Level, offering increased accuracy in contrast to methods which compute the architectural vulnerability of registers through high-level simulations on performance models. Moreover, it does not rely on extensive Statistical Fault Injection (SFI) campaigns and lengthy executions of workloads to completion in RT- or Gate-Level designs, which would make such analysis prohibitive. Instead, it monitors the behavior of key global microprocessor signals in response to a progressive stuck-at fault injection method during partial workload execution. Experimentation with the Scheduler and Reorder Buffer modules of an Alpha-like microprocessor and a modern Intel microprocessor corroborates that GSV analysis generates a near-optimal ranking, yet is several orders of magnitude faster than existing RT- or Gate-Level approaches. |
doi_str_mv | 10.1109/TC.2011.172 |
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In order to effectively allocate design for reliability resources, GSV analysis takes into account the high degree of architectural masking exhibited in modern microprocessors and ranks state elements accordingly. The novelty of this method lies in the way this ranking is computed. GSV analysis operates either at the Register Transfer (RT-) or at the Gate-Level, offering increased accuracy in contrast to methods which compute the architectural vulnerability of registers through high-level simulations on performance models. Moreover, it does not rely on extensive Statistical Fault Injection (SFI) campaigns and lengthy executions of workloads to completion in RT- or Gate-Level designs, which would make such analysis prohibitive. Instead, it monitors the behavior of key global microprocessor signals in response to a progressive stuck-at fault injection method during partial workload execution. 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(IEEE) Oct 2012</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c314t-68eac35838eb5879f3b9fb0802b12815764a6423470efa3198fde30ae363e8843</citedby><cites>FETCH-LOGICAL-c314t-68eac35838eb5879f3b9fb0802b12815764a6423470efa3198fde30ae363e8843</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6280561$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54737</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6280561$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Maniatakos, M.</creatorcontrib><creatorcontrib>Tirumurti, C.</creatorcontrib><creatorcontrib>Galivanche, R.</creatorcontrib><creatorcontrib>Makris, Y.</creatorcontrib><title>Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors</title><title>IEEE transactions on computers</title><addtitle>TC</addtitle><description>Global Signal Vulnerability (GSV) analysis is a novel method for assessing the susceptibility of modern microprocessor state elements to failures in the field of operation. In order to effectively allocate design for reliability resources, GSV analysis takes into account the high degree of architectural masking exhibited in modern microprocessors and ranks state elements accordingly. The novelty of this method lies in the way this ranking is computed. GSV analysis operates either at the Register Transfer (RT-) or at the Gate-Level, offering increased accuracy in contrast to methods which compute the architectural vulnerability of registers through high-level simulations on performance models. Moreover, it does not rely on extensive Statistical Fault Injection (SFI) campaigns and lengthy executions of workloads to completion in RT- or Gate-Level designs, which would make such analysis prohibitive. Instead, it monitors the behavior of key global microprocessor signals in response to a progressive stuck-at fault injection method during partial workload execution. Experimentation with the Scheduler and Reorder Buffer modules of an Alpha-like microprocessor and a modern Intel microprocessor corroborates that GSV analysis generates a near-optimal ranking, yet is several orders of magnitude faster than existing RT- or Gate-Level approaches.</description><subject>Accuracy</subject><subject>Analytical models</subject><subject>AVF</subject><subject>Computational modeling</subject><subject>Computer simulation</subject><subject>control logic</subject><subject>Design engineering</subject><subject>Faults</subject><subject>GSV</subject><subject>Latches</subject><subject>Mathematical models</subject><subject>Microprocessors</subject><subject>modern microprocessor</subject><subject>Ranking</subject><subject>Registers</subject><subject>reliability</subject><subject>Studies</subject><subject>Transient analysis</subject><subject>vulnerability analysis</subject><subject>Workload</subject><issn>0018-9340</issn><issn>1557-9956</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2012</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpd0M9LwzAUB_AgCs7pyaOXgJeJdOZHkybHUeYmTDxs7lrS7nVkZO1MWmH_vRkTD56-h_fhPd4XoXtKxpQS_bLKx4xQOqYZu0ADKkSWaC3kJRoQQlWieUqu0U0IO0KIZEQP0G7m2tI4vLTbJsa6dw14U1pnuyMezZbrJzyJg2OwAdetx0twUHX2G_CyMx3gqYM9NB2eG7-BxjZbbBv83m7Ax7CVbw--rSCE1odbdFUbF-DuN4fo83W6yufJ4mP2lk8WScVp2iVSgam4UFxBKVSma17quiSKsJIyRUUmUyNTxtOMQG041areACcGuOSgVMqHaHTeG09_9RC6Ym9DBc6ZBto-FJRGmcVFItLHf3TX9j7-GxXhItWKaxbV81nFd0LwUBcHb_fGHyMqTr0Xq7w49V7E3qN-OGsLAH9SMkWEpPwHsnN8sw</recordid><startdate>20121001</startdate><enddate>20121001</enddate><creator>Maniatakos, M.</creator><creator>Tirumurti, C.</creator><creator>Galivanche, R.</creator><creator>Makris, Y.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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In order to effectively allocate design for reliability resources, GSV analysis takes into account the high degree of architectural masking exhibited in modern microprocessors and ranks state elements accordingly. The novelty of this method lies in the way this ranking is computed. GSV analysis operates either at the Register Transfer (RT-) or at the Gate-Level, offering increased accuracy in contrast to methods which compute the architectural vulnerability of registers through high-level simulations on performance models. Moreover, it does not rely on extensive Statistical Fault Injection (SFI) campaigns and lengthy executions of workloads to completion in RT- or Gate-Level designs, which would make such analysis prohibitive. Instead, it monitors the behavior of key global microprocessor signals in response to a progressive stuck-at fault injection method during partial workload execution. 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subjects | Accuracy Analytical models AVF Computational modeling Computer simulation control logic Design engineering Faults GSV Latches Mathematical models Microprocessors modern microprocessor Ranking Registers reliability Studies Transient analysis vulnerability analysis Workload |
title | Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors |
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