Synthesizing Multiple Scan Trees to Optimize Test Application Time
This layout-aware, interconnect-driven multiple-scan-tree synthesis methodology applies a density-driven dynamic-clustering algorithm to determine scan cells in each scan tree. The method uses a compatibility-based clique partition algorithm to determine tree topology, and a Voronoi diagram to estab...
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| Veröffentlicht in: | IEEE design & test of computers 2011-03, Vol.28 (2), p.62-69 |
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| container_title | IEEE design & test of computers |
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| creator | Li, K Shu-Min Jr-Yang Huang |
| description | This layout-aware, interconnect-driven multiple-scan-tree synthesis methodology applies a density-driven dynamic-clustering algorithm to determine scan cells in each scan tree. The method uses a compatibility-based clique partition algorithm to determine tree topology, and a Voronoi diagram to establish physical connections. It achieves higher test data compression and far lower test application time, with lower routing length and test power consumption, than previous methods. |
| doi_str_mv | 10.1109/MDT.2011.38 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_1019695091</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5739842</ieee_id><sourcerecordid>2554223051</sourcerecordid><originalsourceid>FETCH-LOGICAL-c313t-84cf7f55dffcce83137bfaa6ab4abbb65e09a5af71b34e1e7b3e322b7147d7923</originalsourceid><addsrcrecordid>eNpd0M1LwzAYBvAgCs7pyaOX4kmQzqRJmuY45yds7LB6Dkn2RjO6tjbtYfvrzZh48PTCy4-Hhweha4InhGD5sHgqJxkmZEKLEzQinBcpkaQ4RSMsGE4FE_wcXYSwwTiqPB-hx9Wu7r8g-L2vP5PFUPW-rSBZWV0nZQcQkr5Jlm3vt34PSQmhT6ZtW3mre99E4rdwic6crgJc_d4x-nh5Lmdv6Xz5-j6bzlNLCe3TglknHOdr56yFIv6EcVrn2jBtjMk5YKm5doIYyoCAMBRolhlBmFgLmdExujvmtl3zPcQmauuDharSNTRDUAQTmUuOJYn09h_dNENXx3ZKEkZxhrMDuj8i2zUhdOBU2_mt7nYxSR3mVHFOdZhT0SLqm6P2APAnuaCyYBn9AcTLcB4</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>914302021</pqid></control><display><type>article</type><title>Synthesizing Multiple Scan Trees to Optimize Test Application Time</title><source>IEEE Electronic Library (IEL)</source><creator>Li, K Shu-Min ; Jr-Yang Huang</creator><creatorcontrib>Li, K Shu-Min ; Jr-Yang Huang</creatorcontrib><description>This layout-aware, interconnect-driven multiple-scan-tree synthesis methodology applies a density-driven dynamic-clustering algorithm to determine scan cells in each scan tree. The method uses a compatibility-based clique partition algorithm to determine tree topology, and a Voronoi diagram to establish physical connections. It achieves higher test data compression and far lower test application time, with lower routing length and test power consumption, than previous methods.</description><identifier>ISSN: 0740-7475</identifier><identifier>ISSN: 2168-2356</identifier><identifier>EISSN: 1558-1918</identifier><identifier>EISSN: 2168-2364</identifier><identifier>DOI: 10.1109/MDT.2011.38</identifier><identifier>CODEN: IDTCEC</identifier><language>eng</language><publisher>Los Alamitos: IEEE Computer Society</publisher><subject>Algorithms ; Compatibility ; Complexity theory ; Computer architecture ; Computers ; Data compression ; design and test ; DFT ; Joints ; Layout ; Power consumption ; Routing ; scan tree ; Silicon ; SoC ; Synthesis ; synthesis methodology ; test application time ; Test data compression ; test data volume ; Topology ; Trees</subject><ispartof>IEEE design & test of computers, 2011-03, Vol.28 (2), p.62-69</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Mar/Apr 2011</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c313t-84cf7f55dffcce83137bfaa6ab4abbb65e09a5af71b34e1e7b3e322b7147d7923</citedby><cites>FETCH-LOGICAL-c313t-84cf7f55dffcce83137bfaa6ab4abbb65e09a5af71b34e1e7b3e322b7147d7923</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5739842$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5739842$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Li, K Shu-Min</creatorcontrib><creatorcontrib>Jr-Yang Huang</creatorcontrib><title>Synthesizing Multiple Scan Trees to Optimize Test Application Time</title><title>IEEE design & test of computers</title><addtitle>MDT</addtitle><description>This layout-aware, interconnect-driven multiple-scan-tree synthesis methodology applies a density-driven dynamic-clustering algorithm to determine scan cells in each scan tree. The method uses a compatibility-based clique partition algorithm to determine tree topology, and a Voronoi diagram to establish physical connections. It achieves higher test data compression and far lower test application time, with lower routing length and test power consumption, than previous methods.</description><subject>Algorithms</subject><subject>Compatibility</subject><subject>Complexity theory</subject><subject>Computer architecture</subject><subject>Computers</subject><subject>Data compression</subject><subject>design and test</subject><subject>DFT</subject><subject>Joints</subject><subject>Layout</subject><subject>Power consumption</subject><subject>Routing</subject><subject>scan tree</subject><subject>Silicon</subject><subject>SoC</subject><subject>Synthesis</subject><subject>synthesis methodology</subject><subject>test application time</subject><subject>Test data compression</subject><subject>test data volume</subject><subject>Topology</subject><subject>Trees</subject><issn>0740-7475</issn><issn>2168-2356</issn><issn>1558-1918</issn><issn>2168-2364</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpd0M1LwzAYBvAgCs7pyaOX4kmQzqRJmuY45yds7LB6Dkn2RjO6tjbtYfvrzZh48PTCy4-Hhweha4InhGD5sHgqJxkmZEKLEzQinBcpkaQ4RSMsGE4FE_wcXYSwwTiqPB-hx9Wu7r8g-L2vP5PFUPW-rSBZWV0nZQcQkr5Jlm3vt34PSQmhT6ZtW3mre99E4rdwic6crgJc_d4x-nh5Lmdv6Xz5-j6bzlNLCe3TglknHOdr56yFIv6EcVrn2jBtjMk5YKm5doIYyoCAMBRolhlBmFgLmdExujvmtl3zPcQmauuDharSNTRDUAQTmUuOJYn09h_dNENXx3ZKEkZxhrMDuj8i2zUhdOBU2_mt7nYxSR3mVHFOdZhT0SLqm6P2APAnuaCyYBn9AcTLcB4</recordid><startdate>201103</startdate><enddate>201103</enddate><creator>Li, K Shu-Min</creator><creator>Jr-Yang Huang</creator><general>IEEE Computer Society</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>201103</creationdate><title>Synthesizing Multiple Scan Trees to Optimize Test Application Time</title><author>Li, K Shu-Min ; Jr-Yang Huang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c313t-84cf7f55dffcce83137bfaa6ab4abbb65e09a5af71b34e1e7b3e322b7147d7923</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Algorithms</topic><topic>Compatibility</topic><topic>Complexity theory</topic><topic>Computer architecture</topic><topic>Computers</topic><topic>Data compression</topic><topic>design and test</topic><topic>DFT</topic><topic>Joints</topic><topic>Layout</topic><topic>Power consumption</topic><topic>Routing</topic><topic>scan tree</topic><topic>Silicon</topic><topic>SoC</topic><topic>Synthesis</topic><topic>synthesis methodology</topic><topic>test application time</topic><topic>Test data compression</topic><topic>test data volume</topic><topic>Topology</topic><topic>Trees</topic><toplevel>online_resources</toplevel><creatorcontrib>Li, K Shu-Min</creatorcontrib><creatorcontrib>Jr-Yang Huang</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE design & test of computers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Li, K Shu-Min</au><au>Jr-Yang Huang</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Synthesizing Multiple Scan Trees to Optimize Test Application Time</atitle><jtitle>IEEE design & test of computers</jtitle><stitle>MDT</stitle><date>2011-03</date><risdate>2011</risdate><volume>28</volume><issue>2</issue><spage>62</spage><epage>69</epage><pages>62-69</pages><issn>0740-7475</issn><issn>2168-2356</issn><eissn>1558-1918</eissn><eissn>2168-2364</eissn><coden>IDTCEC</coden><abstract>This layout-aware, interconnect-driven multiple-scan-tree synthesis methodology applies a density-driven dynamic-clustering algorithm to determine scan cells in each scan tree. The method uses a compatibility-based clique partition algorithm to determine tree topology, and a Voronoi diagram to establish physical connections. It achieves higher test data compression and far lower test application time, with lower routing length and test power consumption, than previous methods.</abstract><cop>Los Alamitos</cop><pub>IEEE Computer Society</pub><doi>10.1109/MDT.2011.38</doi><tpages>8</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Algorithms Compatibility Complexity theory Computer architecture Computers Data compression design and test DFT Joints Layout Power consumption Routing scan tree Silicon SoC Synthesis synthesis methodology test application time Test data compression test data volume Topology Trees |
| title | Synthesizing Multiple Scan Trees to Optimize Test Application Time |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-28T01%3A25%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Synthesizing%20Multiple%20Scan%20Trees%20to%20Optimize%20Test%20Application%20Time&rft.jtitle=IEEE%20design%20&%20test%20of%20computers&rft.au=Li,%20K%20Shu-Min&rft.date=2011-03&rft.volume=28&rft.issue=2&rft.spage=62&rft.epage=69&rft.pages=62-69&rft.issn=0740-7475&rft.eissn=1558-1918&rft.coden=IDTCEC&rft_id=info:doi/10.1109/MDT.2011.38&rft_dat=%3Cproquest_RIE%3E2554223051%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=914302021&rft_id=info:pmid/&rft_ieee_id=5739842&rfr_iscdi=true |