Stackable nonvolatile memory with ultra thin polysilicon film and low-leakage (Ti, Dy) sub(xO) sub(y) for low processing temperature and low operating voltages

We report the fabrication process as well as material and electrical characterization of ultra thin body (UTB) thin film transistors (TFTs) for stackable nonvolatile memories by using in situ phosphorous doped low-temperature polysilicon followed by the chemical mechanical polishing (CMP) process. The resulting polysilicon film is about 13 nm thick with approximately 10 super(19 cm) super(-)3 doping. Root mean square surface roughness below 1 nm is achieved. Metal nanocrystals and high-k dielectric are selected for storage nodes and tunneling barriers to achieve low operating voltages. The number density and average diameter of nanocrystals embedded in the gate stack are 7.5 x 10 super(11 cm) super(-)2 and 5.8 nm, respectively. Furthermore, scanning transmission electron microscopy (STEM), convergent beam electron diffraction (CBED) and electron energy loss spectroscopy (EELS) are performed for material characterization. The dielectric constant of the (Ti, Dy) sub(xO) sub(y) film is 35, and the off-state leakage current at -1 V bias and 2.8 nm equivalent oxide thickness is 5 x 10 super(-7 A/cm) super(2). We obtain a memory window of about 0.95 V with +/-6 V program/erase voltages. Our results show that UTB TFT is a promising candidate for the three-dimensional integration in high-density nonvolatile memory applications.