The fast tracker processor for hadron collider triggers

Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-...

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Veröffentlicht in:	IEEE transactions on nuclear science 2001-06, Vol.48 (3), p.575-580
Hauptverfasser:	Annovi, A., Bagliesi, M.G., Bardi, A., Carosi, R., Dell'Orso, M., D'Onofrio, M., Giannetti, P., Iannaccone, G., Morsani, E., Pietri, M., Varotro, G.
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Banks Benchmarking Collision mitigation Data acquisition Detectors Feasibility Field programmable gate arrays Hadrons Large Hadron Collider Logic Microprocessors Pattern recognition Pipeline processing Roads Searching Tracking Trajectory
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