Design and analysis of a dynamically reconfigurable three-dimensional FPGA
This paper presents the design and analysis of a dynamically reconfigurable field programmable gate array (FPGA) that consists of three physical layers: routing and logic block layer, routing layer, and memory layer. The architecture was developed using a methodology that examines different architec...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2001-02, Vol.9 (1), p.186-196 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Chiricescu, S. Leeser, M. Vai, M.M. |
| description | This paper presents the design and analysis of a dynamically reconfigurable field programmable gate array (FPGA) that consists of three physical layers: routing and logic block layer, routing layer, and memory layer. The architecture was developed using a methodology that examines different architectural parameters and how they affect different performance criteria such as speed, area, and reconfiguration time. The resulting architecture has high performance while the requirement of balancing the areas of its constituent layers is satisfied. |
| doi_str_mv | 10.1109/92.920832 |
| format | Article |
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| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2001-02, Vol.9 (1), p.186-196 |
| issn | 1063-8210 1557-9999 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Architecture Blocking Computer architecture Criteria Design engineering Dynamical systems Field programmable gate arrays Logic design Logic devices Optical interconnections Physical layer Programmable logic arrays Reconfigurable logic Reconfiguration Routing Very large scale integration |
| title | Design and analysis of a dynamically reconfigurable three-dimensional FPGA |
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