ATPG for combinational circuits on configurable hardware

In this paper, a new approach for generating test vectors that detects faults in combinational circuits is introduced. The approach is based on automatically designing a circuit which implements the D-algorithm, an automatic test pattern generation (ATPG) algorithm, specialized for the combinational...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2001-02, Vol.9 (1), p.117-129
Hauptverfasser:	Kocan, F., Saab, D.G.
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithm design and analysis Automatic test pattern generation Circuit faults Circuit testing Circuits Clocks Combinational circuits Costs Electrical fault detection Fault detection Faults Gates (circuits) Hardware Mathematical analysis Pattern generation Vectors (mathematics) Very large scale integration
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