PD/SOI SRAM performance in presence of gate-to-body tunneling current

This paper presents a detailed study on the effects of gate-to-body tunneling current on partially depleted silicon-on-insulator (PD/SOI) CMOS SRAM. It is shown that the presence of gate-to-body tunneling current changes the strength of individual cell transistor in the quiescent (standby) state, th...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2003-12, Vol.11 (6), p.1106-1113
Hauptverfasser:	Joshi, R.V., Ching-Te Chuang, Fung, S.K.H., Assaderaghi, F., Sherony, M., Yang, I., Shahidi, G.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Charge carrier processes Circuits CMOS CMOS technology Degradation Depletion Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Partial discharges Random access memory Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon on insulator technology Static random access memory Temperature Tunneling Very large scale integration Voltage
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