PD/SOI SRAM performance in presence of gate-to-body tunneling current
This paper presents a detailed study on the effects of gate-to-body tunneling current on partially depleted silicon-on-insulator (PD/SOI) CMOS SRAM. It is shown that the presence of gate-to-body tunneling current changes the strength of individual cell transistor in the quiescent (standby) state, th...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2003-12, Vol.11 (6), p.1106-1113 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Joshi, R.V. Ching-Te Chuang Fung, S.K.H. Assaderaghi, F. Sherony, M. Yang, I. Shahidi, G. |
| description | This paper presents a detailed study on the effects of gate-to-body tunneling current on partially depleted silicon-on-insulator (PD/SOI) CMOS SRAM. It is shown that the presence of gate-to-body tunneling current changes the strength of individual cell transistor in the quiescent (standby) state, thus affecting subsequent write/read operations. The degradation in the "write" performance is shown to be more significant than the degradation in the "read" performance, and the effect is more pronounced at lowered temperature. For the beneficial side, the presence of the gate-to-body tunneling current reduces the initial cycle parasitic bipolar disturb from unselected cells on the same bitline during write/read operation. |
| doi_str_mv | 10.1109/TVLSI.2003.817552 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_journals_921473019</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1255484</ieee_id><sourcerecordid>2586703591</sourcerecordid><originalsourceid>FETCH-LOGICAL-c414t-3ca672ed31ffe3aacc624c4a3995cb15056a76e0e78f1a2e4d3ef83480ebe71c3</originalsourceid><addsrcrecordid>eNqFkU1rGzEQhkVpoambH1B6WQptTmtr9K1jSPNhcHGIk1yFLI_ChvWuK-0e8u8jx4FAD-lc5oV55oWZl5BvQKcA1M5u7xer-ZRRyqcGtJTsAzkCKXVtS30smipeGwb0M_mS8yOlIISlR-T8-vdstZxXq5vTP9UOU-zT1ncBq6ardgkz7nUfqwc_YD309brfPFXD2HXYNt1DFcaUsBu-kk_RtxmPX_uE3F2c355d1Yvl5fzsdFEHAWKoefBKM9xwiBG59yEoJoLw3FoZ1iCpVF4rpKhNBM9QbDhGw4WhuEYNgU_IycF3l_q_I-bBbZscsG19h_2YnaXaCm3KrRPy612SWQrKAv8_aKTgSpkC_vgHfOzH1JVznWUgNKdgCwQHKKQ-54TR7VKz9enJAXX7oNxLUG4flDsEVXZ-vhr7HHwbU_l_k98WJbdaMSjc9wPXIOLbmEkpjODPmKiaLA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>921473019</pqid></control><display><type>article</type><title>PD/SOI SRAM performance in presence of gate-to-body tunneling current</title><source>IEEE Electronic Library (IEL)</source><creator>Joshi, R.V. ; Ching-Te Chuang ; Fung, S.K.H. ; Assaderaghi, F. ; Sherony, M. ; Yang, I. ; Shahidi, G.</creator><creatorcontrib>Joshi, R.V. ; Ching-Te Chuang ; Fung, S.K.H. ; Assaderaghi, F. ; Sherony, M. ; Yang, I. ; Shahidi, G.</creatorcontrib><description>This paper presents a detailed study on the effects of gate-to-body tunneling current on partially depleted silicon-on-insulator (PD/SOI) CMOS SRAM. It is shown that the presence of gate-to-body tunneling current changes the strength of individual cell transistor in the quiescent (standby) state, thus affecting subsequent write/read operations. The degradation in the "write" performance is shown to be more significant than the degradation in the "read" performance, and the effect is more pronounced at lowered temperature. For the beneficial side, the presence of the gate-to-body tunneling current reduces the initial cycle parasitic bipolar disturb from unselected cells on the same bitline during write/read operation.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2003.817552</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>Piscataway, NJ: IEEE</publisher><subject>Applied sciences ; Charge carrier processes ; Circuits ; CMOS ; CMOS technology ; Degradation ; Depletion ; Electronics ; Exact sciences and technology ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Partial discharges ; Random access memory ; Semiconductor devices ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Silicon on insulator technology ; Static random access memory ; Temperature ; Tunneling ; Very large scale integration ; Voltage</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2003-12, Vol.11 (6), p.1106-1113</ispartof><rights>2004 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2003</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c414t-3ca672ed31ffe3aacc624c4a3995cb15056a76e0e78f1a2e4d3ef83480ebe71c3</citedby><cites>FETCH-LOGICAL-c414t-3ca672ed31ffe3aacc624c4a3995cb15056a76e0e78f1a2e4d3ef83480ebe71c3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1255484$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27915,27916,54749</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1255484$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=15397621$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Joshi, R.V.</creatorcontrib><creatorcontrib>Ching-Te Chuang</creatorcontrib><creatorcontrib>Fung, S.K.H.</creatorcontrib><creatorcontrib>Assaderaghi, F.</creatorcontrib><creatorcontrib>Sherony, M.</creatorcontrib><creatorcontrib>Yang, I.</creatorcontrib><creatorcontrib>Shahidi, G.</creatorcontrib><title>PD/SOI SRAM performance in presence of gate-to-body tunneling current</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>This paper presents a detailed study on the effects of gate-to-body tunneling current on partially depleted silicon-on-insulator (PD/SOI) CMOS SRAM. It is shown that the presence of gate-to-body tunneling current changes the strength of individual cell transistor in the quiescent (standby) state, thus affecting subsequent write/read operations. The degradation in the "write" performance is shown to be more significant than the degradation in the "read" performance, and the effect is more pronounced at lowered temperature. For the beneficial side, the presence of the gate-to-body tunneling current reduces the initial cycle parasitic bipolar disturb from unselected cells on the same bitline during write/read operation.</description><subject>Applied sciences</subject><subject>Charge carrier processes</subject><subject>Circuits</subject><subject>CMOS</subject><subject>CMOS technology</subject><subject>Degradation</subject><subject>Depletion</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Partial discharges</subject><subject>Random access memory</subject><subject>Semiconductor devices</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Silicon on insulator technology</subject><subject>Static random access memory</subject><subject>Temperature</subject><subject>Tunneling</subject><subject>Very large scale integration</subject><subject>Voltage</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2003</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqFkU1rGzEQhkVpoambH1B6WQptTmtr9K1jSPNhcHGIk1yFLI_ChvWuK-0e8u8jx4FAD-lc5oV55oWZl5BvQKcA1M5u7xer-ZRRyqcGtJTsAzkCKXVtS30smipeGwb0M_mS8yOlIISlR-T8-vdstZxXq5vTP9UOU-zT1ncBq6ardgkz7nUfqwc_YD309brfPFXD2HXYNt1DFcaUsBu-kk_RtxmPX_uE3F2c355d1Yvl5fzsdFEHAWKoefBKM9xwiBG59yEoJoLw3FoZ1iCpVF4rpKhNBM9QbDhGw4WhuEYNgU_IycF3l_q_I-bBbZscsG19h_2YnaXaCm3KrRPy612SWQrKAv8_aKTgSpkC_vgHfOzH1JVznWUgNKdgCwQHKKQ-54TR7VKz9enJAXX7oNxLUG4flDsEVXZ-vhr7HHwbU_l_k98WJbdaMSjc9wPXIOLbmEkpjODPmKiaLA</recordid><startdate>20031201</startdate><enddate>20031201</enddate><creator>Joshi, R.V.</creator><creator>Ching-Te Chuang</creator><creator>Fung, S.K.H.</creator><creator>Assaderaghi, F.</creator><creator>Sherony, M.</creator><creator>Yang, I.</creator><creator>Shahidi, G.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20031201</creationdate><title>PD/SOI SRAM performance in presence of gate-to-body tunneling current</title><author>Joshi, R.V. ; Ching-Te Chuang ; Fung, S.K.H. ; Assaderaghi, F. ; Sherony, M. ; Yang, I. ; Shahidi, G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c414t-3ca672ed31ffe3aacc624c4a3995cb15056a76e0e78f1a2e4d3ef83480ebe71c3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Applied sciences</topic><topic>Charge carrier processes</topic><topic>Circuits</topic><topic>CMOS</topic><topic>CMOS technology</topic><topic>Degradation</topic><topic>Depletion</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Partial discharges</topic><topic>Random access memory</topic><topic>Semiconductor devices</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicon on insulator technology</topic><topic>Static random access memory</topic><topic>Temperature</topic><topic>Tunneling</topic><topic>Very large scale integration</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Joshi, R.V.</creatorcontrib><creatorcontrib>Ching-Te Chuang</creatorcontrib><creatorcontrib>Fung, S.K.H.</creatorcontrib><creatorcontrib>Assaderaghi, F.</creatorcontrib><creatorcontrib>Sherony, M.</creatorcontrib><creatorcontrib>Yang, I.</creatorcontrib><creatorcontrib>Shahidi, G.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Joshi, R.V.</au><au>Ching-Te Chuang</au><au>Fung, S.K.H.</au><au>Assaderaghi, F.</au><au>Sherony, M.</au><au>Yang, I.</au><au>Shahidi, G.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>PD/SOI SRAM performance in presence of gate-to-body tunneling current</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2003-12-01</date><risdate>2003</risdate><volume>11</volume><issue>6</issue><spage>1106</spage><epage>1113</epage><pages>1106-1113</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>This paper presents a detailed study on the effects of gate-to-body tunneling current on partially depleted silicon-on-insulator (PD/SOI) CMOS SRAM. It is shown that the presence of gate-to-body tunneling current changes the strength of individual cell transistor in the quiescent (standby) state, thus affecting subsequent write/read operations. The degradation in the "write" performance is shown to be more significant than the degradation in the "read" performance, and the effect is more pronounced at lowered temperature. For the beneficial side, the presence of the gate-to-body tunneling current reduces the initial cycle parasitic bipolar disturb from unselected cells on the same bitline during write/read operation.</abstract><cop>Piscataway, NJ</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2003.817552</doi><tpages>8</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Charge carrier processes Circuits CMOS CMOS technology Degradation Depletion Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Partial discharges Random access memory Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon on insulator technology Static random access memory Temperature Tunneling Very large scale integration Voltage |
| title | PD/SOI SRAM performance in presence of gate-to-body tunneling current |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T23%3A35%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=PD/SOI%20SRAM%20performance%20in%20presence%20of%20gate-to-body%20tunneling%20current&rft.jtitle=IEEE%20transactions%20on%20very%20large%20scale%20integration%20(VLSI)%20systems&rft.au=Joshi,%20R.V.&rft.date=2003-12-01&rft.volume=11&rft.issue=6&rft.spage=1106&rft.epage=1113&rft.pages=1106-1113&rft.issn=1063-8210&rft.eissn=1557-9999&rft.coden=IEVSE9&rft_id=info:doi/10.1109/TVLSI.2003.817552&rft_dat=%3Cproquest_RIE%3E2586703591%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=921473019&rft_id=info:pmid/&rft_ieee_id=1255484&rfr_iscdi=true |