Ground bounce in digital VLSI circuits
This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitic...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2003-04, Vol.11 (2), p.180-193 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Heydari, P. Pedram, M. |
| description | This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented. |
| doi_str_mv | 10.1109/TVLSI.2003.810785 |
| format | Article |
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First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2003.810785</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>Piscataway, NJ: IEEE</publisher><subject>Applied sciences ; Circuit analysis ; Circuit properties ; Circuits ; CMOS digital integrated circuits ; Compound structure devices ; Decoupling ; Delay ; Design methodology ; Design. Technologies. Operation analysis. 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First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.</description><subject>Applied sciences</subject><subject>Circuit analysis</subject><subject>Circuit properties</subject><subject>Circuits</subject><subject>CMOS digital integrated circuits</subject><subject>Compound structure devices</subject><subject>Decoupling</subject><subject>Delay</subject><subject>Design methodology</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Dielectric, amorphous and glass solid devices</subject><subject>Digital</subject><subject>Digital circuits</subject><subject>Driver circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Grounds</subject><subject>Integrated circuits</subject><subject>Mathematical analysis</subject><subject>Mathematical models</subject><subject>MOS capacitors</subject><subject>MOS devices</subject><subject>Propagation delay</subject><subject>Semiconductor device modeling</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Testing</topic><topic>Dielectric, amorphous and glass solid devices</topic><topic>Digital</topic><topic>Digital circuits</topic><topic>Driver circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Grounds</topic><topic>Integrated circuits</topic><topic>Mathematical analysis</topic><topic>Mathematical models</topic><topic>MOS capacitors</topic><topic>MOS devices</topic><topic>Propagation delay</topic><topic>Semiconductor device modeling</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Switched capacitor circuits</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Heydari, P.</creatorcontrib><creatorcontrib>Pedram, M.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Heydari, P.</au><au>Pedram, M.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Ground bounce in digital VLSI circuits</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2003-04-01</date><risdate>2003</risdate><volume>11</volume><issue>2</issue><spage>180</spage><epage>193</epage><pages>180-193</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.</abstract><cop>Piscataway, NJ</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2003.810785</doi><tpages>14</tpages><oa>free_for_read</oa></addata></record> |
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| identifier | ISSN: 1063-8210 |
| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2003-04, Vol.11 (2), p.180-193 |
| issn | 1063-8210 1557-9999 |
| language | eng |
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| source | IEEE/IET Electronic Library (IEL) |
| subjects | Applied sciences Circuit analysis Circuit properties Circuits CMOS digital integrated circuits Compound structure devices Decoupling Delay Design methodology Design. Technologies. Operation analysis. Testing Dielectric, amorphous and glass solid devices Digital Digital circuits Driver circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Grounds Integrated circuits Mathematical analysis Mathematical models MOS capacitors MOS devices Propagation delay Semiconductor device modeling Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Switched capacitor circuits Very large scale integration |
| title | Ground bounce in digital VLSI circuits |
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