Digital Background-Calibration Algorithm for "Split ADC" Architecture
The ldquosplit ADCrdquo architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the t...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2009-02, Vol.56 (2), p.294-306 |
|---|---|
| Hauptverfasser: | , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 306 |
|---|---|
| container_issue | 2 |
| container_start_page | 294 |
| container_title | IEEE transactions on circuits and systems. I, Regular papers |
| container_volume | 56 |
| creator | McNeill, J.A. Coln, M.C.W. Brown, D.R. Larivee, B.J. |
| description | The ldquosplit ADCrdquo architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background-calibration algorithm. Since both ADCs convert the same input, when correctly calibrated, their outputs should be equal, and the difference should be zero. Any nonzero difference provides information to an error-estimation algorithm, which adjusts digital-calibration parameters in an adaptive process similar to a least mean square algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16-bit 1-MS/s algorithmic cyclic ADC. In addition to correcting ADC linearity, the calibration and estimation algorithms are tolerant of offset error and remove linear scale-factor-error mismatch between the ADC channels. Simulated results are presented confirming self-calibration in approximately 10 000 conversions, which represents an improvement of four orders of magnitude over previous statistically based calibration algorithms. |
| doi_str_mv | 10.1109/TCSI.2008.2001830 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_journals_919707193</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4571117</ieee_id><sourcerecordid>34500228</sourcerecordid><originalsourceid>FETCH-LOGICAL-c422t-338923363ad364bcefdbf6508d8cbed4f5f1de85a5f0e7eea79497286b33a4d43</originalsourceid><addsrcrecordid>eNp9kT1PwzAQhiMEEqXwAxBL1AGxBHz-SOwxpAUqVWJomS0ncVqXtC62M_DvSdSKgYHl7obnPenVE0W3gB4BkHhaFcv5I0aIDwM4QWfRCBjjCeIoPR9uKhJOML-MrrzfIoQFIjCKZlOzNkG18bOqPtfOdvs6KVRrSqeCsfs4b9fWmbDZxY118WR5aE2I82kxiXNXbUzQVeicvo4uGtV6fXPa4-jjZbYq3pLF--u8yBdJRTEOCSFcYEJSomqS0rLSTV02KUO85lWpa9qwBmrNmWIN0pnWKhNUZJinJSGK1pSMo_vj34OzX532Qe6Mr3Tbqr22nZeEsr4Z5j348C8IJGVAMQPUo5M_6NZ2bt_XkAJEhjIQpIfgCFXOeu90Iw_O7JT7loDkIEAOAuQgQJ4E9Jm7Y8ZorX95yjIAyMgPhYt_0g</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>919707193</pqid></control><display><type>article</type><title>Digital Background-Calibration Algorithm for "Split ADC" Architecture</title><source>IEEE Electronic Library (IEL)</source><creator>McNeill, J.A. ; Coln, M.C.W. ; Brown, D.R. ; Larivee, B.J.</creator><creatorcontrib>McNeill, J.A. ; Coln, M.C.W. ; Brown, D.R. ; Larivee, B.J.</creatorcontrib><description>The ldquosplit ADCrdquo architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background-calibration algorithm. Since both ADCs convert the same input, when correctly calibrated, their outputs should be equal, and the difference should be zero. Any nonzero difference provides information to an error-estimation algorithm, which adjusts digital-calibration parameters in an adaptive process similar to a least mean square algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16-bit 1-MS/s algorithmic cyclic ADC. In addition to correcting ADC linearity, the calibration and estimation algorithms are tolerant of offset error and remove linear scale-factor-error mismatch between the ADC channels. Simulated results are presented confirming self-calibration in approximately 10 000 conversions, which represents an improvement of four orders of magnitude over previous statistically based calibration algorithms.</description><identifier>ISSN: 1549-8328</identifier><identifier>EISSN: 1558-0806</identifier><identifier>DOI: 10.1109/TCSI.2008.2001830</identifier><identifier>CODEN: ITCSCH</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Adaptive systems ; Algorithm design and analysis ; Algorithms ; Analog integrated circuits ; analog-digital conversion ; Architecture (computers) ; Calibration ; Channels ; Circuit simulation ; Computer simulation ; Digital ; digital background calibration ; Digital integrated circuits ; Error correction ; Least mean square algorithms ; Least mean squares algorithm ; Least squares approximation ; Linearity ; mixed analog-digital integrated circuits ; self-calibrating ; Signal design ; Studies</subject><ispartof>IEEE transactions on circuits and systems. I, Regular papers, 2009-02, Vol.56 (2), p.294-306</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2009</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c422t-338923363ad364bcefdbf6508d8cbed4f5f1de85a5f0e7eea79497286b33a4d43</citedby><cites>FETCH-LOGICAL-c422t-338923363ad364bcefdbf6508d8cbed4f5f1de85a5f0e7eea79497286b33a4d43</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4571117$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4571117$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>McNeill, J.A.</creatorcontrib><creatorcontrib>Coln, M.C.W.</creatorcontrib><creatorcontrib>Brown, D.R.</creatorcontrib><creatorcontrib>Larivee, B.J.</creatorcontrib><title>Digital Background-Calibration Algorithm for "Split ADC" Architecture</title><title>IEEE transactions on circuits and systems. I, Regular papers</title><addtitle>TCSI</addtitle><description>The ldquosplit ADCrdquo architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background-calibration algorithm. Since both ADCs convert the same input, when correctly calibrated, their outputs should be equal, and the difference should be zero. Any nonzero difference provides information to an error-estimation algorithm, which adjusts digital-calibration parameters in an adaptive process similar to a least mean square algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16-bit 1-MS/s algorithmic cyclic ADC. In addition to correcting ADC linearity, the calibration and estimation algorithms are tolerant of offset error and remove linear scale-factor-error mismatch between the ADC channels. Simulated results are presented confirming self-calibration in approximately 10 000 conversions, which represents an improvement of four orders of magnitude over previous statistically based calibration algorithms.</description><subject>Adaptive systems</subject><subject>Algorithm design and analysis</subject><subject>Algorithms</subject><subject>Analog integrated circuits</subject><subject>analog-digital conversion</subject><subject>Architecture (computers)</subject><subject>Calibration</subject><subject>Channels</subject><subject>Circuit simulation</subject><subject>Computer simulation</subject><subject>Digital</subject><subject>digital background calibration</subject><subject>Digital integrated circuits</subject><subject>Error correction</subject><subject>Least mean square algorithms</subject><subject>Least mean squares algorithm</subject><subject>Least squares approximation</subject><subject>Linearity</subject><subject>mixed analog-digital integrated circuits</subject><subject>self-calibrating</subject><subject>Signal design</subject><subject>Studies</subject><issn>1549-8328</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2009</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kT1PwzAQhiMEEqXwAxBL1AGxBHz-SOwxpAUqVWJomS0ncVqXtC62M_DvSdSKgYHl7obnPenVE0W3gB4BkHhaFcv5I0aIDwM4QWfRCBjjCeIoPR9uKhJOML-MrrzfIoQFIjCKZlOzNkG18bOqPtfOdvs6KVRrSqeCsfs4b9fWmbDZxY118WR5aE2I82kxiXNXbUzQVeicvo4uGtV6fXPa4-jjZbYq3pLF--u8yBdJRTEOCSFcYEJSomqS0rLSTV02KUO85lWpa9qwBmrNmWIN0pnWKhNUZJinJSGK1pSMo_vj34OzX532Qe6Mr3Tbqr22nZeEsr4Z5j348C8IJGVAMQPUo5M_6NZ2bt_XkAJEhjIQpIfgCFXOeu90Iw_O7JT7loDkIEAOAuQgQJ4E9Jm7Y8ZorX95yjIAyMgPhYt_0g</recordid><startdate>20090201</startdate><enddate>20090201</enddate><creator>McNeill, J.A.</creator><creator>Coln, M.C.W.</creator><creator>Brown, D.R.</creator><creator>Larivee, B.J.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20090201</creationdate><title>Digital Background-Calibration Algorithm for "Split ADC" Architecture</title><author>McNeill, J.A. ; Coln, M.C.W. ; Brown, D.R. ; Larivee, B.J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c422t-338923363ad364bcefdbf6508d8cbed4f5f1de85a5f0e7eea79497286b33a4d43</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Adaptive systems</topic><topic>Algorithm design and analysis</topic><topic>Algorithms</topic><topic>Analog integrated circuits</topic><topic>analog-digital conversion</topic><topic>Architecture (computers)</topic><topic>Calibration</topic><topic>Channels</topic><topic>Circuit simulation</topic><topic>Computer simulation</topic><topic>Digital</topic><topic>digital background calibration</topic><topic>Digital integrated circuits</topic><topic>Error correction</topic><topic>Least mean square algorithms</topic><topic>Least mean squares algorithm</topic><topic>Least squares approximation</topic><topic>Linearity</topic><topic>mixed analog-digital integrated circuits</topic><topic>self-calibrating</topic><topic>Signal design</topic><topic>Studies</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>McNeill, J.A.</creatorcontrib><creatorcontrib>Coln, M.C.W.</creatorcontrib><creatorcontrib>Brown, D.R.</creatorcontrib><creatorcontrib>Larivee, B.J.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>McNeill, J.A.</au><au>Coln, M.C.W.</au><au>Brown, D.R.</au><au>Larivee, B.J.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Digital Background-Calibration Algorithm for "Split ADC" Architecture</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2009-02-01</date><risdate>2009</risdate><volume>56</volume><issue>2</issue><spage>294</spage><epage>306</epage><pages>294-306</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>The ldquosplit ADCrdquo architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background-calibration algorithm. Since both ADCs convert the same input, when correctly calibrated, their outputs should be equal, and the difference should be zero. Any nonzero difference provides information to an error-estimation algorithm, which adjusts digital-calibration parameters in an adaptive process similar to a least mean square algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16-bit 1-MS/s algorithmic cyclic ADC. In addition to correcting ADC linearity, the calibration and estimation algorithms are tolerant of offset error and remove linear scale-factor-error mismatch between the ADC channels. Simulated results are presented confirming self-calibration in approximately 10 000 conversions, which represents an improvement of four orders of magnitude over previous statistically based calibration algorithms.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSI.2008.2001830</doi><tpages>13</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1549-8328 |
| ispartof | IEEE transactions on circuits and systems. I, Regular papers, 2009-02, Vol.56 (2), p.294-306 |
| issn | 1549-8328 1558-0806 |
| language | eng |
| recordid | cdi_proquest_journals_919707193 |
| source | IEEE Electronic Library (IEL) |
| subjects | Adaptive systems Algorithm design and analysis Algorithms Analog integrated circuits analog-digital conversion Architecture (computers) Calibration Channels Circuit simulation Computer simulation Digital digital background calibration Digital integrated circuits Error correction Least mean square algorithms Least mean squares algorithm Least squares approximation Linearity mixed analog-digital integrated circuits self-calibrating Signal design Studies |
| title | Digital Background-Calibration Algorithm for "Split ADC" Architecture |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T09%3A02%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Digital%20Background-Calibration%20Algorithm%20for%20%22Split%20ADC%22%20Architecture&rft.jtitle=IEEE%20transactions%20on%20circuits%20and%20systems.%20I,%20Regular%20papers&rft.au=McNeill,%20J.A.&rft.date=2009-02-01&rft.volume=56&rft.issue=2&rft.spage=294&rft.epage=306&rft.pages=294-306&rft.issn=1549-8328&rft.eissn=1558-0806&rft.coden=ITCSCH&rft_id=info:doi/10.1109/TCSI.2008.2001830&rft_dat=%3Cproquest_RIE%3E34500228%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=919707193&rft_id=info:pmid/&rft_ieee_id=4571117&rfr_iscdi=true |