An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets
A layout structure to avoid upsets due to Multiple Cell Upsets (MCUs) is proposed for rad-hard dual-modular Flip-Flops (FFs) called BCDMR (Bistable Cross-coupled Dual-Modular Redundancy) by separating critical components. We have fabricated a 65 nm chip including 30 kbit dual-modular FF arrays on tw...
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| Veröffentlicht in: | IEEE transactions on nuclear science 2011-12, Vol.58 (6), p.3053-3059 |
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| container_title | IEEE transactions on nuclear science |
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| creator | Yamamoto, R. Hamanaka, C. Furuta, J. Kobayashi, K. Onodera, H. |
| description | A layout structure to avoid upsets due to Multiple Cell Upsets (MCUs) is proposed for rad-hard dual-modular Flip-Flops (FFs) called BCDMR (Bistable Cross-coupled Dual-Modular Redundancy) by separating critical components. We have fabricated a 65 nm chip including 30 kbit dual-modular FF arrays on twin-well and triple-well structures. High-energy broad-spectrum neutron irradiations reveal that no soft error is observed up to 100 MHz in the twin-well, but some errors are observed in the triple well. The triple-well structure is sensitive to MCUs because the p-well potential can be easily elevated. |
| doi_str_mv | 10.1109/TNS.2011.2169457 |
| format | Article |
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We have fabricated a 65 nm chip including 30 kbit dual-modular FF arrays on twin-well and triple-well structures. High-energy broad-spectrum neutron irradiations reveal that no soft error is observed up to 100 MHz in the twin-well, but some errors are observed in the triple well. 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(IEEE) Dec 2011</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c389t-774b88c46195ad0618d43ddd63b01bb5f733409ebbba5473cacb4e447be495463</citedby><cites>FETCH-LOGICAL-c389t-774b88c46195ad0618d43ddd63b01bb5f733409ebbba5473cacb4e447be495463</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6093866$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,778,782,794,27907,27908,54741</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6093866$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yamamoto, R.</creatorcontrib><creatorcontrib>Hamanaka, C.</creatorcontrib><creatorcontrib>Furuta, J.</creatorcontrib><creatorcontrib>Kobayashi, K.</creatorcontrib><creatorcontrib>Onodera, H.</creatorcontrib><title>An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets</title><title>IEEE transactions on nuclear science</title><addtitle>TNS</addtitle><description>A layout structure to avoid upsets due to Multiple Cell Upsets (MCUs) is proposed for rad-hard dual-modular Flip-Flops (FFs) called BCDMR (Bistable Cross-coupled Dual-Modular Redundancy) by separating critical components. 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The triple-well structure is sensitive to MCUs because the p-well potential can be easily elevated.</description><subject>65 nm bulk CMOS</subject><subject>Arrays</subject><subject>bi-stable cross-coupled dual-modular (BCDMR)</subject><subject>built-in soft-error resilience (BISER)</subject><subject>Chip formation</subject><subject>CMOS technology</subject><subject>dual-interlocked storage cell (DICE)</subject><subject>Elevated</subject><subject>Errors</subject><subject>flip-flop</subject><subject>Flip-flops</subject><subject>Layout</subject><subject>multiple cell upset (MCU)</subject><subject>Neutron irradiation</subject><subject>Radiation hardening</subject><subject>radiation-hard design</subject><subject>Redundancy</subject><subject>Single event upset</subject><subject>Soft errors</subject><issn>0018-9499</issn><issn>1558-1578</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkEtLAzEUhYMoWKt7wU1w5SY1mTwmWZbaWsEq-Fi5GJJJBiLpZExmBP-9UysuXF0ufOdw-AA4J3hGCFbXLw_PswITMiuIUIyXB2BCOJeI8FIeggnGRCLFlDoGJzm_jy_jmE_A27yF8-Q0WjaNr71reyg4bLfwSVuvex9btNbJwptBB7SJdgg6wVXwHVqF2ME-wvln9BZuhtD7Lji4cCHA1y67Pp-Co0aH7M5-7xS8rpYvizW6f7y9W8zvUU2l6lFZMiNlzQRRXFssiLSMWmsFNZgYw5uSUoaVM8Zozkpa69owx1hpHFOcCToFV_veLsWPweW-2vpcjzt06-KQK4KLQipOftDLf-h7HFI7rqsUGSsZl2qE8B6qU8w5uabqkt_q9DU2VTvZ1Si72smufmWPkYt9xDvn_nCBFZVC0G-uZniN</recordid><startdate>201112</startdate><enddate>201112</enddate><creator>Yamamoto, R.</creator><creator>Hamanaka, C.</creator><creator>Furuta, J.</creator><creator>Kobayashi, K.</creator><creator>Onodera, H.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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| subjects | 65 nm bulk CMOS Arrays bi-stable cross-coupled dual-modular (BCDMR) built-in soft-error resilience (BISER) Chip formation CMOS technology dual-interlocked storage cell (DICE) Elevated Errors flip-flop Flip-flops Layout multiple cell upset (MCU) Neutron irradiation Radiation hardening radiation-hard design Redundancy Single event upset Soft errors |
| title | An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets |
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