A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor
A programmable delay locked loop (DLL) based clock generator, providing a high multiplication factor, has been developed in a 0.18- μm CMOS technology. Utilizing the proposed pulse generator, purely consisting of D flip flops (DFFs) and inverters, the clock generator provides a high multiplication f...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2011-04, Vol.19 (4), p.701-705 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Jaehyouk Choi Kim, S T Woonyun Kim Kwan-Woo Kim Kyutae Lim Laskar, J |
| description | A programmable delay locked loop (DLL) based clock generator, providing a high multiplication factor, has been developed in a 0.18- μm CMOS technology. Utilizing the proposed pulse generator, purely consisting of D flip flops (DFFs) and inverters, the clock generator provides a high multiplication factor of up to 24. It consumes only 16.2 mW when generating 2.16 GHz output signals. In addition, the proposed saturated-type unit delay cell adopted in the voltage controlled delay line (VCDL) is capable of providing a long delay while maintaining fast-switching signal edges. Thus, the DLL can lock up an input reference frequency as low as 30 MHz while maintaining good phase noise performance and small chip area occupancy. The phase noise is -88.7 and -99.8 dBc/Hz at 10 kHz and 100 kHz offsets, respectively, from the operating frequency of 1.2 GHz, which is equivalent to a 1.7 ps RMS jitter. The active chip area takes only 0.051 mm 2 . |
| doi_str_mv | 10.1109/TVLSI.2009.2036433 |
| format | Article |
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Utilizing the proposed pulse generator, purely consisting of D flip flops (DFFs) and inverters, the clock generator provides a high multiplication factor of up to 24. It consumes only 16.2 mW when generating 2.16 GHz output signals. In addition, the proposed saturated-type unit delay cell adopted in the voltage controlled delay line (VCDL) is capable of providing a long delay while maintaining fast-switching signal edges. Thus, the DLL can lock up an input reference frequency as low as 30 MHz while maintaining good phase noise performance and small chip area occupancy. The phase noise is -88.7 and -99.8 dBc/Hz at 10 kHz and 100 kHz offsets, respectively, from the operating frequency of 1.2 GHz, which is equivalent to a 1.7 ps RMS jitter. The active chip area takes only 0.051 mm 2 .</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2009.2036433</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Chips ; Circuit properties ; Circuits of signal characteristics conditioning (including delay circuits) ; Clock generator ; Clock generators ; Clocks ; CMOS technology ; Delay ; delay cell ; delay locked loop (DLL) ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; Dynamic link libraries ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Frequency ; Integrated circuits ; Inverters ; Jitter ; Multiplication ; multiplication factor ; Noise ; Oscillators, resonators, synthetizers ; Phase noise ; Power generation ; programmable ; Pulse generation ; Pulse generators ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Signal generators ; Very large scale integration ; Voltage control</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2011-04, Vol.19 (4), p.701-705</ispartof><rights>2015 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Apr 2011</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c356t-18ded861951626777339fe237d1cf5cacefd7e367e7ea95d97a035815388ca2d3</citedby><cites>FETCH-LOGICAL-c356t-18ded861951626777339fe237d1cf5cacefd7e367e7ea95d97a035815388ca2d3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5356231$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5356231$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=24363571$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Jaehyouk Choi</creatorcontrib><creatorcontrib>Kim, S T</creatorcontrib><creatorcontrib>Woonyun Kim</creatorcontrib><creatorcontrib>Kwan-Woo Kim</creatorcontrib><creatorcontrib>Kyutae Lim</creatorcontrib><creatorcontrib>Laskar, J</creatorcontrib><title>A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>A programmable delay locked loop (DLL) based clock generator, providing a high multiplication factor, has been developed in a 0.18- μm CMOS technology. Utilizing the proposed pulse generator, purely consisting of D flip flops (DFFs) and inverters, the clock generator provides a high multiplication factor of up to 24. It consumes only 16.2 mW when generating 2.16 GHz output signals. In addition, the proposed saturated-type unit delay cell adopted in the voltage controlled delay line (VCDL) is capable of providing a long delay while maintaining fast-switching signal edges. Thus, the DLL can lock up an input reference frequency as low as 30 MHz while maintaining good phase noise performance and small chip area occupancy. The phase noise is -88.7 and -99.8 dBc/Hz at 10 kHz and 100 kHz offsets, respectively, from the operating frequency of 1.2 GHz, which is equivalent to a 1.7 ps RMS jitter. The active chip area takes only 0.051 mm 2 .</description><subject>Applied sciences</subject><subject>Chips</subject><subject>Circuit properties</subject><subject>Circuits of signal characteristics conditioning (including delay circuits)</subject><subject>Clock generator</subject><subject>Clock generators</subject><subject>Clocks</subject><subject>CMOS technology</subject><subject>Delay</subject><subject>delay cell</subject><subject>delay locked loop (DLL)</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Dynamic link libraries</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Frequency</subject><subject>Integrated circuits</subject><subject>Inverters</subject><subject>Jitter</subject><subject>Multiplication</subject><subject>multiplication factor</subject><subject>Noise</subject><subject>Oscillators, resonators, synthetizers</subject><subject>Phase noise</subject><subject>Power generation</subject><subject>programmable</subject><subject>Pulse generation</subject><subject>Pulse generators</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Signal generators</subject><subject>Very large scale integration</subject><subject>Voltage control</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkEtLHEEQgIdgIGryB5JLE5CcRvsx_TrKEnVhRUmMklNT6alZezM7vXbPIv57e91lD9ahqqC-Koqvqr4yesoYtWd397Pf01NOqS1JqEaID9Uhk1LXtsRB6akSteGMfqqOcl5QyprG0sPq7zmZxWdyG58xERha8hBaJL9gmCO5TXGeYLmEfz2SSR_9f3KJAyYYYyrc-EiAXIX5I7le92NY9cHDGOJALsAX4nP1sYM-45ddPa7-XPy8m1zVs5vL6eR8Vnsh1Vgz02JrFLOSKa601kLYDrnQLfOd9OCxazUKpVEjWNlaDVRIw6QwxgNvxXH1Y3t3leLTGvPoliF77HsYMK6zM8oaLi3nhfz-jlzEdRrKc86yhpumkU2B-BbyKeacsHOrFJaQXhyjbuPavbl2G9du57osnewuQ_bQdwkGH_J-kzdCCalZ4b5tuYCI-7EsIrhg4hUsLIZA</recordid><startdate>20110401</startdate><enddate>20110401</enddate><creator>Jaehyouk Choi</creator><creator>Kim, S T</creator><creator>Woonyun Kim</creator><creator>Kwan-Woo Kim</creator><creator>Kyutae Lim</creator><creator>Laskar, J</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Technologies. Operation analysis. Testing</topic><topic>Digital circuits</topic><topic>Dynamic link libraries</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Frequency</topic><topic>Integrated circuits</topic><topic>Inverters</topic><topic>Jitter</topic><topic>Multiplication</topic><topic>multiplication factor</topic><topic>Noise</topic><topic>Oscillators, resonators, synthetizers</topic><topic>Phase noise</topic><topic>Power generation</topic><topic>programmable</topic><topic>Pulse generation</topic><topic>Pulse generators</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Signal generators</topic><topic>Very large scale integration</topic><topic>Voltage control</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Jaehyouk Choi</creatorcontrib><creatorcontrib>Kim, S T</creatorcontrib><creatorcontrib>Woonyun Kim</creatorcontrib><creatorcontrib>Kwan-Woo Kim</creatorcontrib><creatorcontrib>Kyutae Lim</creatorcontrib><creatorcontrib>Laskar, J</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jaehyouk Choi</au><au>Kim, S T</au><au>Woonyun Kim</au><au>Kwan-Woo Kim</au><au>Kyutae Lim</au><au>Laskar, J</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2011-04-01</date><risdate>2011</risdate><volume>19</volume><issue>4</issue><spage>701</spage><epage>705</epage><pages>701-705</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>A programmable delay locked loop (DLL) based clock generator, providing a high multiplication factor, has been developed in a 0.18- μm CMOS technology. Utilizing the proposed pulse generator, purely consisting of D flip flops (DFFs) and inverters, the clock generator provides a high multiplication factor of up to 24. It consumes only 16.2 mW when generating 2.16 GHz output signals. In addition, the proposed saturated-type unit delay cell adopted in the voltage controlled delay line (VCDL) is capable of providing a long delay while maintaining fast-switching signal edges. Thus, the DLL can lock up an input reference frequency as low as 30 MHz while maintaining good phase noise performance and small chip area occupancy. The phase noise is -88.7 and -99.8 dBc/Hz at 10 kHz and 100 kHz offsets, respectively, from the operating frequency of 1.2 GHz, which is equivalent to a 1.7 ps RMS jitter. The active chip area takes only 0.051 mm 2 .</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2009.2036433</doi><tpages>5</tpages></addata></record> |
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| subjects | Applied sciences Chips Circuit properties Circuits of signal characteristics conditioning (including delay circuits) Clock generator Clock generators Clocks CMOS technology Delay delay cell delay locked loop (DLL) Design. Technologies. Operation analysis. Testing Digital circuits Dynamic link libraries Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Frequency Integrated circuits Inverters Jitter Multiplication multiplication factor Noise Oscillators, resonators, synthetizers Phase noise Power generation programmable Pulse generation Pulse generators Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal generators Very large scale integration Voltage control |
| title | A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor |
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