Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform

This paper presents a cost-effective 2-D-discrete cosine transform (DCT) architecture based on the fast row/column decomposition algorithm. We propose a new schedule for 2-D-DCT computing to reduce the hardware cost. With this approach, the transposed memory can be simplified using shift-registers f...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2007-06, Vol.15 (6), p.725-728
Hauptverfasser:	HSIA, Shih-Chang, WANG, Szu-Hong
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Applied sciences Architecture Arrays Circuit design Circuit properties Circuits Computer architecture Computing costs Costs Dielectric, amorphous and glass solid devices Digital circuits Discrete cosine transform Discrete cosine transform (DCT) Discrete cosine transforms Discrete transforms Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Frequency Hardware Processor scheduling pseudo capacitor Read-write memory row/column decomposition Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices shift register Size control Transformations Transistors Very large scale integration video coding
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