Multiple-Gate CMOS Thin-Film Transistor With Polysilicon Nanowire
An ultimately scaled multiple-gate CMOS thin-film transistor with a polysilicon (poly-Si) nanowire demonstrates feasibility for vertical integration using multiple active layers for application in the terabit memory era. The short-channel effects are suppressed using a multiple gate to wrap around t...
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| Veröffentlicht in: | IEEE electron device letters 2008-01, Vol.29 (1), p.102-105 |
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| container_end_page | 105 |
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| container_title | IEEE electron device letters |
| container_volume | 29 |
| creator | IM, Maesoon HAN, Jin-Woo YUN CHANG PARK HEE MOK LEE CHOI, Yang-Kyu LEE, Hyunjin YU, Lee-Eun KIM, Sungho KIM, Chang-Hoon SANG CHEOL JEON KWANG HEE KIM GI SUNG LEE JAE SUB OH |
| description | An ultimately scaled multiple-gate CMOS thin-film transistor with a polysilicon (poly-Si) nanowire demonstrates feasibility for vertical integration using multiple active layers for application in the terabit memory era. The short-channel effects are suppressed using a multiple gate to wrap around the nanowire in devices with a size of a few tenths of a nanometer. The switching and output characteristics show high device performance without a crystallization process for the poly-Si nanowire. |
| doi_str_mv | 10.1109/LED.2007.911982 |
| format | Article |
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The short-channel effects are suppressed using a multiple gate to wrap around the nanowire in devices with a size of a few tenths of a nanometer. The switching and output characteristics show high device performance without a crystallization process for the poly-Si nanowire.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2007.911982</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; CMOS ; Consumer electronics ; Crystallization ; Delay effects ; Design. Technologies. Operation analysis. Testing ; Devices ; Dielectrics ; Electronics ; Energy consumption ; Exact sciences and technology ; Grain boundaries ; Grain size ; Integrated circuits ; Memory ; multiple gate ; Nanocomposites ; Nanomaterials ; nanoscale ; Nanoscale devices ; Nanostructure ; nanowire ; Nanowires ; Semiconductor devices ; Semiconductor electronics. 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(IEEE) 2008</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c344t-fe86e5453ec6613990bdfd3e8b656a4bbaccee5d2aefd202ce1b9e8c0af0c1a83</citedby><cites>FETCH-LOGICAL-c344t-fe86e5453ec6613990bdfd3e8b656a4bbaccee5d2aefd202ce1b9e8c0af0c1a83</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4408732$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,4024,27923,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4408732$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=19954383$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>IM, Maesoon</creatorcontrib><creatorcontrib>HAN, Jin-Woo</creatorcontrib><creatorcontrib>YUN CHANG PARK</creatorcontrib><creatorcontrib>HEE MOK LEE</creatorcontrib><creatorcontrib>CHOI, Yang-Kyu</creatorcontrib><creatorcontrib>LEE, Hyunjin</creatorcontrib><creatorcontrib>YU, Lee-Eun</creatorcontrib><creatorcontrib>KIM, Sungho</creatorcontrib><creatorcontrib>KIM, Chang-Hoon</creatorcontrib><creatorcontrib>SANG CHEOL JEON</creatorcontrib><creatorcontrib>KWANG HEE KIM</creatorcontrib><creatorcontrib>GI SUNG LEE</creatorcontrib><creatorcontrib>JAE SUB OH</creatorcontrib><title>Multiple-Gate CMOS Thin-Film Transistor With Polysilicon Nanowire</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>An ultimately scaled multiple-gate CMOS thin-film transistor with a polysilicon (poly-Si) nanowire demonstrates feasibility for vertical integration using multiple active layers for application in the terabit memory era. The short-channel effects are suppressed using a multiple gate to wrap around the nanowire in devices with a size of a few tenths of a nanometer. The switching and output characteristics show high device performance without a crystallization process for the poly-Si nanowire.</description><subject>Applied sciences</subject><subject>CMOS</subject><subject>Consumer electronics</subject><subject>Crystallization</subject><subject>Delay effects</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Devices</subject><subject>Dielectrics</subject><subject>Electronics</subject><subject>Energy consumption</subject><subject>Exact sciences and technology</subject><subject>Grain boundaries</subject><subject>Grain size</subject><subject>Integrated circuits</subject><subject>Memory</subject><subject>multiple gate</subject><subject>Nanocomposites</subject><subject>Nanomaterials</subject><subject>nanoscale</subject><subject>Nanoscale devices</subject><subject>Nanostructure</subject><subject>nanowire</subject><subject>Nanowires</subject><subject>Semiconductor devices</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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(IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>200801</creationdate><title>Multiple-Gate CMOS Thin-Film Transistor With Polysilicon Nanowire</title><author>IM, Maesoon ; HAN, Jin-Woo ; YUN CHANG PARK ; HEE MOK LEE ; CHOI, Yang-Kyu ; LEE, Hyunjin ; YU, Lee-Eun ; KIM, Sungho ; KIM, Chang-Hoon ; SANG CHEOL JEON ; KWANG HEE KIM ; GI SUNG LEE ; JAE SUB OH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c344t-fe86e5453ec6613990bdfd3e8b656a4bbaccee5d2aefd202ce1b9e8c0af0c1a83</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Applied sciences</topic><topic>CMOS</topic><topic>Consumer electronics</topic><topic>Crystallization</topic><topic>Delay effects</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Devices</topic><topic>Dielectrics</topic><topic>Electronics</topic><topic>Energy consumption</topic><topic>Exact sciences and technology</topic><topic>Grain boundaries</topic><topic>Grain size</topic><topic>Integrated circuits</topic><topic>Memory</topic><topic>multiple gate</topic><topic>Nanocomposites</topic><topic>Nanomaterials</topic><topic>nanoscale</topic><topic>Nanoscale devices</topic><topic>Nanostructure</topic><topic>nanowire</topic><topic>Nanowires</topic><topic>Semiconductor devices</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. 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| identifier | ISSN: 0741-3106 |
| ispartof | IEEE electron device letters, 2008-01, Vol.29 (1), p.102-105 |
| issn | 0741-3106 1558-0563 |
| language | eng |
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| source | IEEE Electronic Library Online |
| subjects | Applied sciences CMOS Consumer electronics Crystallization Delay effects Design. Technologies. Operation analysis. Testing Devices Dielectrics Electronics Energy consumption Exact sciences and technology Grain boundaries Grain size Integrated circuits Memory multiple gate Nanocomposites Nanomaterials nanoscale Nanoscale devices Nanostructure nanowire Nanowires Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Switching Thin film transistors Thin films thin-film transistor (TFT) Transistors vertical integration |
| title | Multiple-Gate CMOS Thin-Film Transistor With Polysilicon Nanowire |
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