Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation

In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased st...

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Veröffentlicht in:	IEEE transactions on nanotechnology 2006-05, Vol.5 (3), p.180-185
Hauptverfasser:	Cho, Seongjae, Park, Il Han, Kim, Tae Hun, Sim, Jae Sung, Song, Ki-Whan, Lee, Jong Duk, Shin, Hyungcheol, Park, Byung-Gook
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Computer simulation Design optimization Design. Technologies. Operation analysis. Testing Disturbances Electronics Exact sciences and technology Flash memory Flash memory (computers) Flash memory cells Integrated circuits Integrated circuits by function (including memories and processors) Magnetic and optical mass memories Mathematical models MOSFET circuits MOSFETs Nonvolatile memory Numerical simulation Operating schemes Optimization Predictive models Random access memory read disturbance Retarding Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon Silicon nitride Storage and reproduction of information Thickness control Transistors Tunneling two-bit floating-gate-type nonvolative memory (NVM) cell
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