Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation
In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased st...
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| Veröffentlicht in: | IEEE transactions on nanotechnology 2006-05, Vol.5 (3), p.180-185 |
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| container_title | IEEE transactions on nanotechnology |
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| creator | Cho, Seongjae Park, Il Han Kim, Tae Hun Sim, Jae Sung Song, Ki-Whan Lee, Jong Duk Shin, Hyungcheol Park, Byung-Gook |
| description | In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased states are found to be the crucial factors that put the NVM cell operation under optimum condition. Under fairly good conditions, the silicon thickness can reach below 30 nm while suppressing the read disturbance level within 1 V. With these results, operating schemes are investigated for both NAND - and NOR-type memory cells. This paper is based on simulation works which can give a reasonable intuition in flash memory operation. Although we adopted a floating-gate-type device since the exact modeling of Si/sub 3/N/sub 4/ used for the storage node is absent in the current numerical simulator, this helps to predict the operation of an oxide-nitride-oxide dielectric flash memory cell at a good degree. |
| doi_str_mv | 10.1109/TNANO.2006.869943 |
| format | Article |
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The thickness and the difference of charge amount between programmed and erased states are found to be the crucial factors that put the NVM cell operation under optimum condition. Under fairly good conditions, the silicon thickness can reach below 30 nm while suppressing the read disturbance level within 1 V. With these results, operating schemes are investigated for both NAND - and NOR-type memory cells. This paper is based on simulation works which can give a reasonable intuition in flash memory operation. Although we adopted a floating-gate-type device since the exact modeling of Si/sub 3/N/sub 4/ used for the storage node is absent in the current numerical simulator, this helps to predict the operation of an oxide-nitride-oxide dielectric flash memory cell at a good degree.</description><identifier>ISSN: 1536-125X</identifier><identifier>EISSN: 1941-0085</identifier><identifier>DOI: 10.1109/TNANO.2006.869943</identifier><identifier>CODEN: ITNECU</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Computer simulation ; Design optimization ; Design. Technologies. Operation analysis. Testing ; Disturbances ; Electronics ; Exact sciences and technology ; Flash memory ; Flash memory (computers) ; Flash memory cells ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Magnetic and optical mass memories ; Mathematical models ; MOSFET circuits ; MOSFETs ; Nonvolatile memory ; Numerical simulation ; Operating schemes ; Optimization ; Predictive models ; Random access memory ; read disturbance ; Retarding ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Silicon ; Silicon nitride ; Storage and reproduction of information ; Thickness control ; Transistors ; Tunneling ; two-bit floating-gate-type nonvolative memory (NVM) cell</subject><ispartof>IEEE transactions on nanotechnology, 2006-05, Vol.5 (3), p.180-185</ispartof><rights>2006 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2006</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c451t-59c2fe47da0bad0ed49795021ac75d34e6ff3227d8e901e69781005faf04597b3</citedby><cites>FETCH-LOGICAL-c451t-59c2fe47da0bad0ed49795021ac75d34e6ff3227d8e901e69781005faf04597b3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1632131$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,780,784,789,790,796,23929,23930,25139,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1632131$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=17821973$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Cho, Seongjae</creatorcontrib><creatorcontrib>Park, Il Han</creatorcontrib><creatorcontrib>Kim, Tae Hun</creatorcontrib><creatorcontrib>Sim, Jae Sung</creatorcontrib><creatorcontrib>Song, Ki-Whan</creatorcontrib><creatorcontrib>Lee, Jong Duk</creatorcontrib><creatorcontrib>Shin, Hyungcheol</creatorcontrib><creatorcontrib>Park, Byung-Gook</creatorcontrib><title>Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation</title><title>IEEE transactions on nanotechnology</title><addtitle>TNANO</addtitle><description>In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased states are found to be the crucial factors that put the NVM cell operation under optimum condition. Under fairly good conditions, the silicon thickness can reach below 30 nm while suppressing the read disturbance level within 1 V. With these results, operating schemes are investigated for both NAND - and NOR-type memory cells. This paper is based on simulation works which can give a reasonable intuition in flash memory operation. Although we adopted a floating-gate-type device since the exact modeling of Si/sub 3/N/sub 4/ used for the storage node is absent in the current numerical simulator, this helps to predict the operation of an oxide-nitride-oxide dielectric flash memory cell at a good degree.</description><subject>Applied sciences</subject><subject>Computer simulation</subject><subject>Design optimization</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Disturbances</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Flash memory</subject><subject>Flash memory (computers)</subject><subject>Flash memory cells</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Magnetic and optical mass memories</subject><subject>Mathematical models</subject><subject>MOSFET circuits</subject><subject>MOSFETs</subject><subject>Nonvolatile memory</subject><subject>Numerical simulation</subject><subject>Operating schemes</subject><subject>Optimization</subject><subject>Predictive models</subject><subject>Random access memory</subject><subject>read disturbance</subject><subject>Retarding</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Silicon</subject><subject>Silicon nitride</subject><subject>Storage and reproduction of information</subject><subject>Thickness control</subject><subject>Transistors</subject><subject>Tunneling</subject><subject>two-bit floating-gate-type nonvolative memory (NVM) cell</subject><issn>1536-125X</issn><issn>1941-0085</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kV1rFDEUhgdRsFZ_gHgTBPVq1nMyk6_LUj-htDcVvAvZmZNtSmayJrOV9deb7RYKXniVA3neh3N4m-Y1wgoRzMfry7PLqxUHkCstjem7J80Jmh5bAC2e1ll0skUufj5vXpRyC4BKCn3SjJ-ohM3M3DyytF3CFP64JaSZJc-W36ldh4WNabeO1G7cQmxO812KFYnEJppS3rOBYmQ-ZXYTNjdxzzLF4Gqg-ijfy142z7yLhV49vKfNjy-fr8-_tRdXX7-fn120Qy9waYUZuKdejQ7WbgQae6OMAI5uUGLsepLed5yrUZMBJGmURgDhnYdeGLXuTpsPR-82p187KoudQjms52ZKu2K1kSiN5LKS7_9Lcg1gOqUq-PYf8Dbt8lyvsAY5ByW4rhAeoSGnUjJ5u81hcnlvEeyhHntfjz3UY4_11My7B7Erg4s-u3kI5TGoNEejDtybIxeI6PFbdhw77P4CJOSZJw</recordid><startdate>20060501</startdate><enddate>20060501</enddate><creator>Cho, Seongjae</creator><creator>Park, Il Han</creator><creator>Kim, Tae Hun</creator><creator>Sim, Jae Sung</creator><creator>Song, Ki-Whan</creator><creator>Lee, Jong Duk</creator><creator>Shin, Hyungcheol</creator><creator>Park, Byung-Gook</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Technologies. Operation analysis. Testing</topic><topic>Disturbances</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Flash memory</topic><topic>Flash memory (computers)</topic><topic>Flash memory cells</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Magnetic and optical mass memories</topic><topic>Mathematical models</topic><topic>MOSFET circuits</topic><topic>MOSFETs</topic><topic>Nonvolatile memory</topic><topic>Numerical simulation</topic><topic>Operating schemes</topic><topic>Optimization</topic><topic>Predictive models</topic><topic>Random access memory</topic><topic>read disturbance</topic><topic>Retarding</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicon</topic><topic>Silicon nitride</topic><topic>Storage and reproduction of information</topic><topic>Thickness control</topic><topic>Transistors</topic><topic>Tunneling</topic><topic>two-bit floating-gate-type nonvolative memory (NVM) cell</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Cho, Seongjae</creatorcontrib><creatorcontrib>Park, Il Han</creatorcontrib><creatorcontrib>Kim, Tae Hun</creatorcontrib><creatorcontrib>Sim, Jae Sung</creatorcontrib><creatorcontrib>Song, Ki-Whan</creatorcontrib><creatorcontrib>Lee, Jong Duk</creatorcontrib><creatorcontrib>Shin, Hyungcheol</creatorcontrib><creatorcontrib>Park, Byung-Gook</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Engineered Materials Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>Materials Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on nanotechnology</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Cho, Seongjae</au><au>Park, Il Han</au><au>Kim, Tae Hun</au><au>Sim, Jae Sung</au><au>Song, Ki-Whan</au><au>Lee, Jong Duk</au><au>Shin, Hyungcheol</au><au>Park, Byung-Gook</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation</atitle><jtitle>IEEE transactions on nanotechnology</jtitle><stitle>TNANO</stitle><date>2006-05-01</date><risdate>2006</risdate><volume>5</volume><issue>3</issue><spage>180</spage><epage>185</epage><pages>180-185</pages><issn>1536-125X</issn><eissn>1941-0085</eissn><coden>ITNECU</coden><abstract>In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased states are found to be the crucial factors that put the NVM cell operation under optimum condition. Under fairly good conditions, the silicon thickness can reach below 30 nm while suppressing the read disturbance level within 1 V. With these results, operating schemes are investigated for both NAND - and NOR-type memory cells. This paper is based on simulation works which can give a reasonable intuition in flash memory operation. Although we adopted a floating-gate-type device since the exact modeling of Si/sub 3/N/sub 4/ used for the storage node is absent in the current numerical simulator, this helps to predict the operation of an oxide-nitride-oxide dielectric flash memory cell at a good degree.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TNANO.2006.869943</doi><tpages>6</tpages></addata></record> |
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| subjects | Applied sciences Computer simulation Design optimization Design. Technologies. Operation analysis. Testing Disturbances Electronics Exact sciences and technology Flash memory Flash memory (computers) Flash memory cells Integrated circuits Integrated circuits by function (including memories and processors) Magnetic and optical mass memories Mathematical models MOSFET circuits MOSFETs Nonvolatile memory Numerical simulation Operating schemes Optimization Predictive models Random access memory read disturbance Retarding Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon Silicon nitride Storage and reproduction of information Thickness control Transistors Tunneling two-bit floating-gate-type nonvolative memory (NVM) cell |
| title | Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation |
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