A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications
In this paper, a low-cost H.264/AVC video decoder design is presented for high definition television (HDTV) applications. Through optimization from algorithmic and architectural perspectives, the proposed design can achieve real-time H.264 video decoding on HD1080 video (1920 times 1088@30 Hz) when...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2007-01, Vol.42 (1), p.170-182 |
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| container_title | IEEE journal of solid-state circuits |
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| creator | LIN, Chien-Chang CHEN, Jia-Wei CHANG, Hsiu-Cheng YANG, Yao-Chang YANG, Yi-Huan Ou TSAI, Ming-Chih GUO, Jiun-In WANG, Jinn-Shyan |
| description | In this paper, a low-cost H.264/AVC video decoder design is presented for high definition television (HDTV) applications. Through optimization from algorithmic and architectural perspectives, the proposed design can achieve real-time H.264 video decoding on HD1080 video (1920 times 1088@30 Hz) when operating at 120 MHz with 320 mW power dissipation. Fabricated by using the TSMC one-poly six-metal 0.18 mum CMOS technology, the proposed design occupies 2.9times2.9 mm 2 silicon area with the hardware complexity of 160K gates and 4.5K bytes of local memory |
| doi_str_mv | 10.1109/JSSC.2006.886537 |
| format | Article |
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Testing</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Gates</subject><subject>H264/AVC video decoder architecture design</subject><subject>Hardware</subject><subject>HDTV</subject><subject>High definition television</subject><subject>High definition video</subject><subject>Imaging devices</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>low power consumption</subject><subject>low-cost design</subject><subject>Optimization</subject><subject>Power dissipation</subject><subject>Random access memory</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Technologies. Operation analysis. Testing</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Gates</topic><topic>H264/AVC video decoder architecture design</topic><topic>Hardware</topic><topic>HDTV</topic><topic>High definition television</topic><topic>High definition video</topic><topic>Imaging devices</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>low power consumption</topic><topic>low-cost design</topic><topic>Optimization</topic><topic>Power dissipation</topic><topic>Random access memory</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. 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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2007-01, Vol.42 (1), p.170-182 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Algorithm design and analysis Applied sciences Automatic voltage control Circuit properties Circuits CMOS CMOS technology Decoders Decoding Design optimization Design. Technologies. Operation analysis. Testing Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Gates H264/AVC video decoder architecture design Hardware HDTV High definition television High definition video Imaging devices Integrated circuits Integrated circuits by function (including memories and processors) low power consumption low-cost design Optimization Power dissipation Random access memory Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal convertors |
| title | A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications |
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