Yield Prediction for Integrated Circuits Manufacturing Through Hierarchical Bayesian Modeling of Spatial Defects

Accurate yield prediction to evaluate productivity, and to estimate production costs, is a critical issue in the highly competitive semiconductor industry. We propose yield models based on hierarchical Bayesian modeling of clustered spatial defects produced in integrated circuits (IC) manufacturing....

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Veröffentlicht in:	IEEE transactions on reliability 2011-12, Vol.60 (4), p.729-741
Hauptverfasser:	Tao Yuan, Ramadan, S. Z., Bae, S. J.
Format:	Artikel
Sprache:	eng
Schlagworte:	Bayesian methods Data models Hierarchical bayesian model Integrated circuit manufacture Integrated circuit modeling Mathematical models Semiconductor device modeling spatial defects Studies Yield estimation yield prediction zero-inflated models
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