Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits
In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize, and monitor spatially-correlated inter-die and/or intra-die variations in nanoscale manufacturing process. VP exploits recent breakthroughs in compressed sensing to accurately predict...
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Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2011-12, Vol.30 (12), p.1814-1827 |
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