Area-efficient VLSI layouts for binary hypercubes

The hypercube is an interesting and useful topology for parallel computation. While hypercubes have been analyzed in graph theory, this analysis has done little to determine the minimum area required for realizations of the hypercube topology on two-dimensional chips. In a common VLSI layout of the...

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Veröffentlicht in:	IEEE transactions on computers 2000-02, Vol.49 (2), p.160-169
Hauptverfasser:	Patel, A., Kusalik, A., McCrosky, C.
Format:	Artikel
Sprache:	eng
Schlagworte:	Concurrent computing Graph theory Greedy algorithms Hypercubes Integrated circuits Mathematical models Optimization Order disorder Parallel algorithms Studies Switches Topology Two dimensional Upper bound Very large scale integration Wiring
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