Static power modeling of 32-bit microprocessors

The paper presents a novel strategy aimed at modeling instruction energy consumption of 32-bit microprocessors. Different from former approaches, the proposed instruction-level power model is founded on a functional decomposition of the activities accomplished by a generic microprocessor. The propos...

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Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems 2002-11, Vol.21 (11), p.1306-1316
Hauptverfasser: Brandolese, C., Salice, F., Fornaciari, W., Sciuto, D.
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container_title IEEE transactions on computer-aided design of integrated circuits and systems
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creator Brandolese, C.
Salice, F.
Fornaciari, W.
Sciuto, D.
description The paper presents a novel strategy aimed at modeling instruction energy consumption of 32-bit microprocessors. Different from former approaches, the proposed instruction-level power model is founded on a functional decomposition of the activities accomplished by a generic microprocessor. The proposed model has significant generalization capabilities. It allows estimation of the power figures of the entire instruction-set starting from the analysis of a subset, as well as to power characterize new processors by using the model obtained by considering other microprocessors. The model is formally presented and justified and its actual application over five commercial microprocessors is included. This static characterization is the basic information for system-level power modeling of hardware/software architectures.
doi_str_mv 10.1109/TCAD.2002.804104
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subjects Application software
Computer aided design
Computer programs
Costs
Design engineering
Embedded software
Energy consumption
Hardware
Microprocessors
Power system modeling
Processors
Software
Software architecture
Strategy
Time to market
title Static power modeling of 32-bit microprocessors
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