System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints

Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource conflicts, and limit power dissipation during test mode. In this paper, we present an integrated approach to several test...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2002-09, Vol.21 (9), p.1088-1094
Hauptverfasser:	Iyengar, V., Chakrabarty, K.
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Automatic testing Automation Computer aided design Design engineering Heuristic algorithms Job shop scheduling Optimal scheduling Optimization Polynomials Power dissipation Preserves Schedules Scheduling Scheduling algorithm System on chip System testing System-on-a-chip
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