A method enabling feasible conformance test sequence generation for EFSM models

A formal description of an implementation under test (IUT), such as its VHDL behavior description, is required to automatically generate feasible test sequences for the IUT. Although finite-state machines (FSMs) can be used to describe the control structures of communication protocols, the data port...

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Veröffentlicht in:	IEEE transactions on computers 2004-05, Vol.53 (5), p.614-627
Hauptverfasser:	Duale, A.Y., Uyar, M.U.
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Complexity theory Conformance testing Finite state machines Graph theory Hardware design languages Protocols Software packages Studies
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