Modeling and optimization of substrate resistance for RF-CMOS
A predictive, physically based substrate resistance model for CMOS transistors operating at radio frequencies (RF) is described. This analytical model is scalable with transistor size and layout geometry. Measurement results confirm that the model accurately predicts the effect of substrate resistan...
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| Veröffentlicht in: | IEEE transactions on electron devices 2004-03, Vol.51 (3), p.421-426 |
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| container_end_page | 426 |
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| container_issue | 3 |
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| container_title | IEEE transactions on electron devices |
| container_volume | 51 |
| creator | Chang, R.T. Ming-Ta Yang Ho, P.P.C. Yo-Jen Wang Yu-Tai Chia Boon-Khim Liew Yue, C.P. Wong, S.S. |
| description | A predictive, physically based substrate resistance model for CMOS transistors operating at radio frequencies (RF) is described. This analytical model is scalable with transistor size and layout geometry. Measurement results confirm that the model accurately predicts the effect of substrate resistance on the transistor output impedance up to 20 GHz, including gate and drain bias dependencies. Minimization of the substrate resistance can be achieved by using substrate tap rings with small spacer distances and short finger widths. |
| doi_str_mv | 10.1109/TED.2003.822586 |
| format | Article |
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This analytical model is scalable with transistor size and layout geometry. Measurement results confirm that the model accurately predicts the effect of substrate resistance on the transistor output impedance up to 20 GHz, including gate and drain bias dependencies. Minimization of the substrate resistance can be achieved by using substrate tap rings with small spacer distances and short finger widths.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2003.822586</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>CMOS ; CMOS integrated circuits ; Contact resistance ; Drains ; Fingers ; Mathematical models ; Optimization ; Radio frequencies ; Semiconductor devices ; Transistors</subject><ispartof>IEEE transactions on electron devices, 2004-03, Vol.51 (3), p.421-426</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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This analytical model is scalable with transistor size and layout geometry. Measurement results confirm that the model accurately predicts the effect of substrate resistance on the transistor output impedance up to 20 GHz, including gate and drain bias dependencies. Minimization of the substrate resistance can be achieved by using substrate tap rings with small spacer distances and short finger widths.</description><subject>CMOS</subject><subject>CMOS integrated circuits</subject><subject>Contact resistance</subject><subject>Drains</subject><subject>Fingers</subject><subject>Mathematical models</subject><subject>Optimization</subject><subject>Radio frequencies</subject><subject>Semiconductor devices</subject><subject>Transistors</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqNkc1Lw0AQxRdRsFbPHrwED3pKnd1s9uPgQWqrQktB63nZJBNJabN1NznoX--WCoIHEQaGgd8beO8Rck5hRCnom-XkfsQAspFiLFfigAxonstUCy4OyQCAqlRnKjsmJyGs4ik4ZwNyO3cVrpv2LbFtlbht12yaT9s1rk1cnYS-CJ23HSYeQxM625aY1M4nz9N0PF-8nJKj2q4Dnn3vIXmdTpbjx3S2eHga383SknPRpQKKspBcS4kWoZQCda5rzQEkqzVVylZa1goYqJxhDZAXuqykrCCXFmWWDcn1_u_Wu_ceQ2c2TShxvbYtuj4YHe0oyUFG8upPkinNdEbpP8AslzHICF7-Aleu9220a5TiMXnBWYRu9lDpXQgea7P1zcb6D0PB7OoxsR6zq8fs64mKi72iQcQfmgkVJ_sCv_2ImA</recordid><startdate>20040301</startdate><enddate>20040301</enddate><creator>Chang, R.T.</creator><creator>Ming-Ta Yang</creator><creator>Ho, P.P.C.</creator><creator>Yo-Jen Wang</creator><creator>Yu-Tai Chia</creator><creator>Boon-Khim Liew</creator><creator>Yue, C.P.</creator><creator>Wong, S.S.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20040301</creationdate><title>Modeling and optimization of substrate resistance for RF-CMOS</title><author>Chang, R.T. ; Ming-Ta Yang ; Ho, P.P.C. ; Yo-Jen Wang ; Yu-Tai Chia ; Boon-Khim Liew ; Yue, C.P. ; Wong, S.S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c446t-60bcb74977eae0c76e959f940072f9188ad97f8020852ef005b9cd77d057ae733</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2004</creationdate><topic>CMOS</topic><topic>CMOS integrated circuits</topic><topic>Contact resistance</topic><topic>Drains</topic><topic>Fingers</topic><topic>Mathematical models</topic><topic>Optimization</topic><topic>Radio frequencies</topic><topic>Semiconductor devices</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chang, R.T.</creatorcontrib><creatorcontrib>Ming-Ta Yang</creatorcontrib><creatorcontrib>Ho, P.P.C.</creatorcontrib><creatorcontrib>Yo-Jen Wang</creatorcontrib><creatorcontrib>Yu-Tai Chia</creatorcontrib><creatorcontrib>Boon-Khim Liew</creatorcontrib><creatorcontrib>Yue, C.P.</creatorcontrib><creatorcontrib>Wong, S.S.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chang, R.T.</au><au>Ming-Ta Yang</au><au>Ho, P.P.C.</au><au>Yo-Jen Wang</au><au>Yu-Tai Chia</au><au>Boon-Khim Liew</au><au>Yue, C.P.</au><au>Wong, S.S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Modeling and optimization of substrate resistance for RF-CMOS</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2004-03-01</date><risdate>2004</risdate><volume>51</volume><issue>3</issue><spage>421</spage><epage>426</epage><pages>421-426</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>A predictive, physically based substrate resistance model for CMOS transistors operating at radio frequencies (RF) is described. This analytical model is scalable with transistor size and layout geometry. Measurement results confirm that the model accurately predicts the effect of substrate resistance on the transistor output impedance up to 20 GHz, including gate and drain bias dependencies. Minimization of the substrate resistance can be achieved by using substrate tap rings with small spacer distances and short finger widths.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2003.822586</doi><tpages>6</tpages></addata></record> |
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| ispartof | IEEE transactions on electron devices, 2004-03, Vol.51 (3), p.421-426 |
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| language | eng |
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| subjects | CMOS CMOS integrated circuits Contact resistance Drains Fingers Mathematical models Optimization Radio frequencies Semiconductor devices Transistors |
| title | Modeling and optimization of substrate resistance for RF-CMOS |
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