Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller

We investigate the correlation between low-level faults in the control logic of a modern microprocessor and their instruction-level impact on the execution of typical workload. Such information can prove immensely useful in accurately assessing and prioritizing faults with regards to their criticali...

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Veröffentlicht in:	IEEE transactions on computers 2011-09, Vol.60 (9), p.1260-1273
Hauptverfasser:	Maniatakos, M., Karimi, N., Tirumurti, C., Jas, A., Makris, Y.
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuit faults Clocks Computer simulation concurrent error detection Error detection Errors Fault simulation Faults Hardware design languages Infrastructure instruction-level error Logic Logic gates microprocessor controller Microprocessors Permissible error Transient analysis Wire
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