Image display processing system for high definition television

This paper proposes an image display processing system that reduces the core performance of the processor allocated in the image display, thereby enabling the use of a less expensive low-performance processor. Essentially, the proposed system supports a high-resolution image display function in an electronic picture frame (EPF) module using a low-performance processor based on converting HD image data at a 15 Hz frame rate into HD image data at a 60 Hz frame rate for use in a digital TV system. As a result, the proposed system can reduce the processor performance to a level corresponding to an image display with a low frame rate, thereby reducing the product cost and allowing various additional functions. Finally, the proposed system is implemented to confirm its effectiveness.