Optimal register sharing for high-level synthesis of SSA form programs
Register sharing for high-level synthesis of programs represented in static single assignment (SSA) form is proven to have a polynomial-time solution. Register sharing is modeled as a graph-coloring problem. Although graph coloring is NP-Complete in the general case, an interference graph constructe...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2006-05, Vol.25 (5), p.772-779 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
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| creator | Brisk, P. Dabiri, F. Jafari, R. Sarrafzadeh, M. |
| description | Register sharing for high-level synthesis of programs represented in static single assignment (SSA) form is proven to have a polynomial-time solution. Register sharing is modeled as a graph-coloring problem. Although graph coloring is NP-Complete in the general case, an interference graph constructed for a program in SSA form probably belongs to the class of chordal graphs that have an optimal O(|V|+|E|) time algorithm. Chordal graph coloring reduces the number of registers allocated to the program by as much as 86% and 64.93% on average compared to linear scan register allocation. |
| doi_str_mv | 10.1109/TCAD.2006.870409 |
| format | Article |
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Register sharing is modeled as a graph-coloring problem. Although graph coloring is NP-Complete in the general case, an interference graph constructed for a program in SSA form probably belongs to the class of chordal graphs that have an optimal O(|V|+|E|) time algorithm. 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Register sharing is modeled as a graph-coloring problem. Although graph coloring is NP-Complete in the general case, an interference graph constructed for a program in SSA form probably belongs to the class of chordal graphs that have an optimal O(|V|+|E|) time algorithm. Chordal graph coloring reduces the number of registers allocated to the program by as much as 86% and 64.93% on average compared to linear scan register allocation.</description><subject>Compilers (silicon)</subject><subject>Computer aided design</subject><subject>Computer science</subject><subject>Design engineering</subject><subject>Flow graphs</subject><subject>Graphs</subject><subject>High level synthesis</subject><subject>Integrated circuits</subject><subject>Interference</subject><subject>Interference graphs</subject><subject>Optimal control</subject><subject>Optimization</subject><subject>Polynomials</subject><subject>Processor scheduling</subject><subject>Registers</subject><subject>Resource management</subject><subject>Silicon</subject><subject>Synthesis</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqFkUtLAzEUhYMoWKt7wU1woaupN89JlqVaFQpdtPswj8yjzHRqMhX6780wguBCV3dxvnNfB6FbAjNCQD9tF_PnGQWQMxUDB32GJkSzOOJEkHM0ARqrCCCGS3Tl_Q6AcEH1BC3Xh75ukwY7W9a-tw77KnH1vsRF53BVl1XU2E_bYH_a95X1tcddgTeb-aC3-OC60iWtv0YXRdJ4e_Ndp2i7fNku3qLV-vV9MV9FGaeyjwqqhc1TIWPFwkKpTjLNRZqnFhQQwWSaM57FKsgyFnkeCyFB5IyBFRnTbIoex7Zh7sfR-t60tc9s0yR72x29UVoSTTnlgXz4kwyLSK6B_Q8qkIpwGcD7X-CuO7p9uNYoKaQAyiBAMEKZ67x3tjAHF97rToaAGXIyQ05myMmMOQXL3WiprbU_uKRcEMK-ABcSjBE</recordid><startdate>200605</startdate><enddate>200605</enddate><creator>Brisk, P.</creator><creator>Dabiri, F.</creator><creator>Jafari, R.</creator><creator>Sarrafzadeh, M.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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| source | IEEE Electronic Library (IEL) |
| subjects | Compilers (silicon) Computer aided design Computer science Design engineering Flow graphs Graphs High level synthesis Integrated circuits Interference Interference graphs Optimal control Optimization Polynomials Processor scheduling Registers Resource management Silicon Synthesis |
| title | Optimal register sharing for high-level synthesis of SSA form programs |
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