Exploiting Process Locality of Reference in RTL Simulation Acceleration

With the increased size and complexity of digital designs, the time required to simulate them has also increased. Traditional simulation accelerators utilize FPGAs in a static configuration, but this paper presents an analysis of six register transfer level (RTL) code bases showing that only a subse...

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Veröffentlicht in:	EURASIP journal on embedded systems 2008, Vol.2008, p.1-10
Hauptverfasser:	Blumer, Aric D., Patterson, Cameron D.
Format:	Artikel
Sprache:	eng
Schlagworte:	Behavior Design Field programmable gate arrays Integrated circuits Simulation
Online-Zugang:	Volltext
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