A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package
Input-output buffer information specification BIS (IBIS) models are descriptions of the output buffers, used by the printed circuit board (PCB) designer to evaluate the integrity and the quality of the signals. The extension of the use of IBIS models to the system in package (SiP) world is considere...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2008-08, Vol.55 (7), p.1921-1928 |
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| container_end_page | 1928 |
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| container_issue | 7 |
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| container_title | IEEE transactions on circuits and systems. I, Regular papers |
| container_volume | 55 |
| creator | Pulici, P. Girardi, A. Vanalli, G.P. Izzi, R. Bernardi, G. Ripamonti, G. Strollo, A. Campardo, G. |
| description | Input-output buffer information specification BIS (IBIS) models are descriptions of the output buffers, used by the printed circuit board (PCB) designer to evaluate the integrity and the quality of the signals. The extension of the use of IBIS models to the system in package (SiP) world is considered. It is found that IBIS models demonstrate some limits for this application, mainly due to the poor stabilization of the supply voltage rails. An example highlighting the IBIS model limits is given. A simple hand analysis of the phenomenon is performed, from which we derive a simple solution to the problem, consisting in an improvement of the structure of the IBIS model. Simulations run making use of the improved models show a much better accuracy of the signal shapes, within 5% of the simulations run with a state-of-the-art transistor level description of the buffers. |
| doi_str_mv | 10.1109/TCSI.2008.918203 |
| format | Article |
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The extension of the use of IBIS models to the system in package (SiP) world is considered. It is found that IBIS models demonstrate some limits for this application, mainly due to the poor stabilization of the supply voltage rails. An example highlighting the IBIS model limits is given. A simple hand analysis of the phenomenon is performed, from which we derive a simple solution to the problem, consisting in an improvement of the structure of the IBIS model. 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(IEEE) 2008</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c353t-2e4820a30b7591cbec2462e43d364f9d10580a7d559e705e9d4e3ae72f03d1b73</citedby><cites>FETCH-LOGICAL-c353t-2e4820a30b7591cbec2462e43d364f9d10580a7d559e705e9d4e3ae72f03d1b73</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4599149$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4599149$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Pulici, P.</creatorcontrib><creatorcontrib>Girardi, A.</creatorcontrib><creatorcontrib>Vanalli, G.P.</creatorcontrib><creatorcontrib>Izzi, R.</creatorcontrib><creatorcontrib>Bernardi, G.</creatorcontrib><creatorcontrib>Ripamonti, G.</creatorcontrib><creatorcontrib>Strollo, A.</creatorcontrib><creatorcontrib>Campardo, G.</creatorcontrib><title>A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package</title><title>IEEE transactions on circuits and systems. I, Regular papers</title><addtitle>TCSI</addtitle><description>Input-output buffer information specification BIS (IBIS) models are descriptions of the output buffers, used by the printed circuit board (PCB) designer to evaluate the integrity and the quality of the signals. The extension of the use of IBIS models to the system in package (SiP) world is considered. It is found that IBIS models demonstrate some limits for this application, mainly due to the poor stabilization of the supply voltage rails. An example highlighting the IBIS model limits is given. A simple hand analysis of the phenomenon is performed, from which we derive a simple solution to the problem, consisting in an improvement of the structure of the IBIS model. Simulations run making use of the improved models show a much better accuracy of the signal shapes, within 5% of the simulations run with a state-of-the-art transistor level description of the buffers.</description><subject>Buffer circuits</subject><subject>Buffers</subject><subject>Circuit boards</subject><subject>circuit modeling</subject><subject>Circuit simulation</subject><subject>Computer simulation</subject><subject>Crosstalk</subject><subject>Descriptions</subject><subject>driver circuits</subject><subject>Electric potential</subject><subject>electromagnetic interferences</subject><subject>Information analysis</subject><subject>Integrated circuit modeling</subject><subject>Integrated circuit packaging</subject><subject>interconnections</subject><subject>Mathematical models</subject><subject>Packages</subject><subject>Printed circuits</subject><subject>Signal analysis</subject><subject>Signal design</subject><subject>Voltage</subject><subject>Wire</subject><issn>1549-8328</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2008</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kbtPwzAQxi0EEqWwI7FYDDClnF-JPZaKR6TykFrmyE0ulUvalDgd8t_jKIiBgem7O_3upY-QSwYTxsDcLWeLdMIB9MQwzUEckRFTSkegIT7uY2kiLbg-JWfebwC4AcFG5HVKX-rClQ4Lmt6niz7Dik7dNhRsSxduvbMVTXctrhvXdnQa0s47T-uSLjrf4tZTt6PvNv-0azwnJ6WtPF786Jh8PD4sZ8_R_O0pnU3nUS6UaCOOMtxoBawSZVi-wpzLOBRFIWJZmoKB0mCTQimDCSg0hURhMeEliIKtEjEmt8PcfVN_HdC32db5HKvK7rA--EyHr2VsmAnkzb-kkApiZXrw-g-4qQ9N-DZMiwUXQgcZExigvKm9b7DM9o3b2qbLGGS9D1nvQ9b7kA0-hJarocUh4i8uw0omjfgGX22A7A</recordid><startdate>20080801</startdate><enddate>20080801</enddate><creator>Pulici, P.</creator><creator>Girardi, A.</creator><creator>Vanalli, G.P.</creator><creator>Izzi, R.</creator><creator>Bernardi, G.</creator><creator>Ripamonti, G.</creator><creator>Strollo, A.</creator><creator>Campardo, G.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Pulici, P.</au><au>Girardi, A.</au><au>Vanalli, G.P.</au><au>Izzi, R.</au><au>Bernardi, G.</au><au>Ripamonti, G.</au><au>Strollo, A.</au><au>Campardo, G.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2008-08-01</date><risdate>2008</risdate><volume>55</volume><issue>7</issue><spage>1921</spage><epage>1928</epage><pages>1921-1928</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>Input-output buffer information specification BIS (IBIS) models are descriptions of the output buffers, used by the printed circuit board (PCB) designer to evaluate the integrity and the quality of the signals. The extension of the use of IBIS models to the system in package (SiP) world is considered. It is found that IBIS models demonstrate some limits for this application, mainly due to the poor stabilization of the supply voltage rails. An example highlighting the IBIS model limits is given. A simple hand analysis of the phenomenon is performed, from which we derive a simple solution to the problem, consisting in an improvement of the structure of the IBIS model. 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| source | IEEE Electronic Library (IEL) |
| subjects | Buffer circuits Buffers Circuit boards circuit modeling Circuit simulation Computer simulation Crosstalk Descriptions driver circuits Electric potential electromagnetic interferences Information analysis Integrated circuit modeling Integrated circuit packaging interconnections Mathematical models Packages Printed circuits Signal analysis Signal design Voltage Wire |
| title | A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package |
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