A Full On-Chip CMOS Clock-and-Data Recovery IC for OC-192 Applications
In this paper, a fully integrated OC-192 clock-and-data recovery (CDR) architecture in standard 0.18-mum CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET j...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2008-06, Vol.55 (5), p.1213-1222 |
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| container_issue | 5 |
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| container_title | IEEE transactions on circuits and systems. I, Regular papers |
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| creator | Jinghua Li Silva-Martinez, J. Brunn, B. Rokhsaz, S. Robinson, M.E. |
| description | In this paper, a fully integrated OC-192 clock-and-data recovery (CDR) architecture in standard 0.18-mum CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290 mW. The measured RMS jitter of the recovered data is 0.74 ps with a bit-error rate less than 10 -12 when the input pseudorandom bit sequence (PRBS) data pattern has a pattern length of 2 15 - 1 and a total horizontal eye closure of 0.54 peak-to-peak unit interval (Ul pp ) due to the added intersymbol interference distortion by passing data through 9-in FR4 printed circuit board trace. The chip exceeds SONET OC-192 jitter tolerance mask, and high-frequency jitter tolerance is over 0.31 Ul pp by applying PRBS data with a pattern length of 2 31 - 1. |
| doi_str_mv | 10.1109/TCSI.2008.916439 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_journals_863232558</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4435085</ieee_id><sourcerecordid>880651920</sourcerecordid><originalsourceid>FETCH-LOGICAL-c353t-7a661abe9d7e4b924b5b4b23579a4e162ab1b84f8335eec05a5537092a7254013</originalsourceid><addsrcrecordid>eNp9kD1PwzAQhi0EEqWwI7FYDDC5nL8Se6wChUpFkWiZLSd1RUqIQ5wg9d-TKIiBgelueN7TvQ9ClxRmlIK-2yTr5YwBqJmmkeD6CE2olIqAguh42IUmijN1is5C2AMwDZxO0GKOF11Z4rQiyVtR4-Q5XeOk9Pk7sdWW3NvW4heX-y_XHPAywTvf4DQhVDM8r-uyyG1b-Cqco5OdLYO7-JlT9Lp42CRPZJU-LpP5iuRc8pbENoqozZzexk5kmolMZiJjXMbaCkcjZjOaKbFTnEvncpBWSh6DZjZmUgDlU3Q73q0b_9m50JqPIuSuLG3lfBeM6tvK_jnoyZt_SS4kyEjHPXj9B9z7rqn6FkZFnHHWW-whGKG88SE0bmfqpviwzcFQMIN_M_g3g38z-u8jV2OkcM794kJwCUryb5cdfCw</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>863232558</pqid></control><display><type>article</type><title>A Full On-Chip CMOS Clock-and-Data Recovery IC for OC-192 Applications</title><source>IEEE Electronic Library (IEL)</source><creator>Jinghua Li ; Silva-Martinez, J. ; Brunn, B. ; Rokhsaz, S. ; Robinson, M.E.</creator><creatorcontrib>Jinghua Li ; Silva-Martinez, J. ; Brunn, B. ; Rokhsaz, S. ; Robinson, M.E.</creatorcontrib><description>In this paper, a fully integrated OC-192 clock-and-data recovery (CDR) architecture in standard 0.18-mum CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290 mW. The measured RMS jitter of the recovered data is 0.74 ps with a bit-error rate less than 10 -12 when the input pseudorandom bit sequence (PRBS) data pattern has a pattern length of 2 15 - 1 and a total horizontal eye closure of 0.54 peak-to-peak unit interval (Ul pp ) due to the added intersymbol interference distortion by passing data through 9-in FR4 printed circuit board trace. The chip exceeds SONET OC-192 jitter tolerance mask, and high-frequency jitter tolerance is over 0.31 Ul pp by applying PRBS data with a pattern length of 2 31 - 1.</description><identifier>ISSN: 1549-8328</identifier><identifier>EISSN: 1558-0806</identifier><identifier>DOI: 10.1109/TCSI.2008.916439</identifier><identifier>CODEN: ITCSCH</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Application specific integrated circuits ; Architecture ; Capacitors ; Circuit boards ; Clock-and-data (CDR) recovery circuits ; Clocks ; CMOS ; CMOS integrated circuits ; data communication circuits ; Feedforward systems ; Filters ; full on-chip CDR ; Horizontal ; Intervals ; Jitter ; monolithic CDRs ; OC-192 ; phase-locked loops (PLLs) ; Poles and zeros ; Power generation ; Recovery ; SONET ; Tolerances</subject><ispartof>IEEE transactions on circuits and systems. I, Regular papers, 2008-06, Vol.55 (5), p.1213-1222</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2008</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c353t-7a661abe9d7e4b924b5b4b23579a4e162ab1b84f8335eec05a5537092a7254013</citedby><cites>FETCH-LOGICAL-c353t-7a661abe9d7e4b924b5b4b23579a4e162ab1b84f8335eec05a5537092a7254013</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4435085$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4435085$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jinghua Li</creatorcontrib><creatorcontrib>Silva-Martinez, J.</creatorcontrib><creatorcontrib>Brunn, B.</creatorcontrib><creatorcontrib>Rokhsaz, S.</creatorcontrib><creatorcontrib>Robinson, M.E.</creatorcontrib><title>A Full On-Chip CMOS Clock-and-Data Recovery IC for OC-192 Applications</title><title>IEEE transactions on circuits and systems. I, Regular papers</title><addtitle>TCSI</addtitle><description>In this paper, a fully integrated OC-192 clock-and-data recovery (CDR) architecture in standard 0.18-mum CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290 mW. The measured RMS jitter of the recovered data is 0.74 ps with a bit-error rate less than 10 -12 when the input pseudorandom bit sequence (PRBS) data pattern has a pattern length of 2 15 - 1 and a total horizontal eye closure of 0.54 peak-to-peak unit interval (Ul pp ) due to the added intersymbol interference distortion by passing data through 9-in FR4 printed circuit board trace. The chip exceeds SONET OC-192 jitter tolerance mask, and high-frequency jitter tolerance is over 0.31 Ul pp by applying PRBS data with a pattern length of 2 31 - 1.</description><subject>Application specific integrated circuits</subject><subject>Architecture</subject><subject>Capacitors</subject><subject>Circuit boards</subject><subject>Clock-and-data (CDR) recovery circuits</subject><subject>Clocks</subject><subject>CMOS</subject><subject>CMOS integrated circuits</subject><subject>data communication circuits</subject><subject>Feedforward systems</subject><subject>Filters</subject><subject>full on-chip CDR</subject><subject>Horizontal</subject><subject>Intervals</subject><subject>Jitter</subject><subject>monolithic CDRs</subject><subject>OC-192</subject><subject>phase-locked loops (PLLs)</subject><subject>Poles and zeros</subject><subject>Power generation</subject><subject>Recovery</subject><subject>SONET</subject><subject>Tolerances</subject><issn>1549-8328</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2008</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kD1PwzAQhi0EEqWwI7FYDDC5nL8Se6wChUpFkWiZLSd1RUqIQ5wg9d-TKIiBgelueN7TvQ9ClxRmlIK-2yTr5YwBqJmmkeD6CE2olIqAguh42IUmijN1is5C2AMwDZxO0GKOF11Z4rQiyVtR4-Q5XeOk9Pk7sdWW3NvW4heX-y_XHPAywTvf4DQhVDM8r-uyyG1b-Cqco5OdLYO7-JlT9Lp42CRPZJU-LpP5iuRc8pbENoqozZzexk5kmolMZiJjXMbaCkcjZjOaKbFTnEvncpBWSh6DZjZmUgDlU3Q73q0b_9m50JqPIuSuLG3lfBeM6tvK_jnoyZt_SS4kyEjHPXj9B9z7rqn6FkZFnHHWW-whGKG88SE0bmfqpviwzcFQMIN_M_g3g38z-u8jV2OkcM794kJwCUryb5cdfCw</recordid><startdate>20080601</startdate><enddate>20080601</enddate><creator>Jinghua Li</creator><creator>Silva-Martinez, J.</creator><creator>Brunn, B.</creator><creator>Rokhsaz, S.</creator><creator>Robinson, M.E.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20080601</creationdate><title>A Full On-Chip CMOS Clock-and-Data Recovery IC for OC-192 Applications</title><author>Jinghua Li ; Silva-Martinez, J. ; Brunn, B. ; Rokhsaz, S. ; Robinson, M.E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c353t-7a661abe9d7e4b924b5b4b23579a4e162ab1b84f8335eec05a5537092a7254013</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Application specific integrated circuits</topic><topic>Architecture</topic><topic>Capacitors</topic><topic>Circuit boards</topic><topic>Clock-and-data (CDR) recovery circuits</topic><topic>Clocks</topic><topic>CMOS</topic><topic>CMOS integrated circuits</topic><topic>data communication circuits</topic><topic>Feedforward systems</topic><topic>Filters</topic><topic>full on-chip CDR</topic><topic>Horizontal</topic><topic>Intervals</topic><topic>Jitter</topic><topic>monolithic CDRs</topic><topic>OC-192</topic><topic>phase-locked loops (PLLs)</topic><topic>Poles and zeros</topic><topic>Power generation</topic><topic>Recovery</topic><topic>SONET</topic><topic>Tolerances</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Jinghua Li</creatorcontrib><creatorcontrib>Silva-Martinez, J.</creatorcontrib><creatorcontrib>Brunn, B.</creatorcontrib><creatorcontrib>Rokhsaz, S.</creatorcontrib><creatorcontrib>Robinson, M.E.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jinghua Li</au><au>Silva-Martinez, J.</au><au>Brunn, B.</au><au>Rokhsaz, S.</au><au>Robinson, M.E.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Full On-Chip CMOS Clock-and-Data Recovery IC for OC-192 Applications</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2008-06-01</date><risdate>2008</risdate><volume>55</volume><issue>5</issue><spage>1213</spage><epage>1222</epage><pages>1213-1222</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>In this paper, a fully integrated OC-192 clock-and-data recovery (CDR) architecture in standard 0.18-mum CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290 mW. The measured RMS jitter of the recovered data is 0.74 ps with a bit-error rate less than 10 -12 when the input pseudorandom bit sequence (PRBS) data pattern has a pattern length of 2 15 - 1 and a total horizontal eye closure of 0.54 peak-to-peak unit interval (Ul pp ) due to the added intersymbol interference distortion by passing data through 9-in FR4 printed circuit board trace. The chip exceeds SONET OC-192 jitter tolerance mask, and high-frequency jitter tolerance is over 0.31 Ul pp by applying PRBS data with a pattern length of 2 31 - 1.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSI.2008.916439</doi><tpages>10</tpages></addata></record> |
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| identifier | ISSN: 1549-8328 |
| ispartof | IEEE transactions on circuits and systems. I, Regular papers, 2008-06, Vol.55 (5), p.1213-1222 |
| issn | 1549-8328 1558-0806 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Application specific integrated circuits Architecture Capacitors Circuit boards Clock-and-data (CDR) recovery circuits Clocks CMOS CMOS integrated circuits data communication circuits Feedforward systems Filters full on-chip CDR Horizontal Intervals Jitter monolithic CDRs OC-192 phase-locked loops (PLLs) Poles and zeros Power generation Recovery SONET Tolerances |
| title | A Full On-Chip CMOS Clock-and-Data Recovery IC for OC-192 Applications |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T07%3A34%3A04IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20Full%20On-Chip%20CMOS%20Clock-and-Data%20Recovery%20IC%20for%20OC-192%20Applications&rft.jtitle=IEEE%20transactions%20on%20circuits%20and%20systems.%20I,%20Regular%20papers&rft.au=Jinghua%20Li&rft.date=2008-06-01&rft.volume=55&rft.issue=5&rft.spage=1213&rft.epage=1222&rft.pages=1213-1222&rft.issn=1549-8328&rft.eissn=1558-0806&rft.coden=ITCSCH&rft_id=info:doi/10.1109/TCSI.2008.916439&rft_dat=%3Cproquest_RIE%3E880651920%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=863232558&rft_id=info:pmid/&rft_ieee_id=4435085&rfr_iscdi=true |