Automatic Fault Localization for Property Checking

We present an efficient fully automatic approach to fault localization for safety properties stated in linear temporal logic. We view the failure as a contradiction between the specification and the actual behavior and look for components that explain this discrepancy. We find these components by so...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2008-06, Vol.27 (6), p.1138-1149
Hauptverfasser:	Fey, G., Staber, S., Bloem, R., Drechsler, R.
Format:	Artikel
Sprache:	eng
Schlagworte:	Automatic logic units Circuit faults Circuit simulation Computational efficiency Computer simulation Computing time Debugging Failure Fault diagnosis Faults Formal verification Hardware design languages Localization Position (location) Preprocessing Safety satisfiability checking sequential circuit fault diagnosis Sequential circuits
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