Automatic Fault Localization for Property Checking
We present an efficient fully automatic approach to fault localization for safety properties stated in linear temporal logic. We view the failure as a contradiction between the specification and the actual behavior and look for components that explain this discrepancy. We find these components by so...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2008-06, Vol.27 (6), p.1138-1149 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
| container_volume | 27 |
| creator | Fey, G. Staber, S. Bloem, R. Drechsler, R. |
| description | We present an efficient fully automatic approach to fault localization for safety properties stated in linear temporal logic. We view the failure as a contradiction between the specification and the actual behavior and look for components that explain this discrepancy. We find these components by solving the satisfiability of a propositional Boolean formula. We show how to construct this formula and how to extend it so that we find exactly those components that can be used to repair the circuit for a given set of counterexamples. Furthermore, we discuss how to efficiently solve the formula by using the proper decision heuristics and simulation-based preprocessing. We demonstrate the quality and efficiency of our approach by experimental results. |
| doi_str_mv | 10.1109/TCAD.2008.923234 |
| format | Article |
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We view the failure as a contradiction between the specification and the actual behavior and look for components that explain this discrepancy. We find these components by solving the satisfiability of a propositional Boolean formula. We show how to construct this formula and how to extend it so that we find exactly those components that can be used to repair the circuit for a given set of counterexamples. Furthermore, we discuss how to efficiently solve the formula by using the proper decision heuristics and simulation-based preprocessing. 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We view the failure as a contradiction between the specification and the actual behavior and look for components that explain this discrepancy. We find these components by solving the satisfiability of a propositional Boolean formula. We show how to construct this formula and how to extend it so that we find exactly those components that can be used to repair the circuit for a given set of counterexamples. Furthermore, we discuss how to efficiently solve the formula by using the proper decision heuristics and simulation-based preprocessing. We demonstrate the quality and efficiency of our approach by experimental results.</description><subject>Automatic logic units</subject><subject>Circuit faults</subject><subject>Circuit simulation</subject><subject>Computational efficiency</subject><subject>Computer simulation</subject><subject>Computing time</subject><subject>Debugging</subject><subject>Failure</subject><subject>Fault diagnosis</subject><subject>Faults</subject><subject>Formal verification</subject><subject>Hardware design languages</subject><subject>Localization</subject><subject>Position (location)</subject><subject>Preprocessing</subject><subject>Safety</subject><subject>satisfiability checking</subject><subject>sequential circuit fault diagnosis</subject><subject>Sequential circuits</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2008</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkD1PwzAURS0EEuVjR2KJWJhS3rOd2B6rQAGpEgxlthzHgZQ0LnYylF9PqiAGpiddnXv1dAi5QpgjgrpbF4v7OQWQc0UZZfyIzFAxkXLM8JjMgAqZAgg4JWcxbgCQZ1TNCF0Mvd-avrHJ0gxtn6y8NW3zPSa-S2ofktfgdy70-6T4cPaz6d4vyElt2uguf-85eVs-rIundPXy-FwsVqllUvYpqrpmGYB1EmleWeBGVMi4UAatxRJcSavKGkkNVKJSQmQUyrIurctMzgU7J7fT7i74r8HFXm-baF3bms75IWopMhC5otlI3vwjN34I3ficljkVOUjJRggmyAYfY3C13oVma8JeI-iDQn1QqA8K9aRwrFxPlcY594eP4nLBkf0Ahb5r1w</recordid><startdate>20080601</startdate><enddate>20080601</enddate><creator>Fey, G.</creator><creator>Staber, S.</creator><creator>Bloem, R.</creator><creator>Drechsler, R.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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We view the failure as a contradiction between the specification and the actual behavior and look for components that explain this discrepancy. We find these components by solving the satisfiability of a propositional Boolean formula. We show how to construct this formula and how to extend it so that we find exactly those components that can be used to repair the circuit for a given set of counterexamples. Furthermore, we discuss how to efficiently solve the formula by using the proper decision heuristics and simulation-based preprocessing. We demonstrate the quality and efficiency of our approach by experimental results.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCAD.2008.923234</doi><tpages>12</tpages></addata></record> |
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| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 2008-06, Vol.27 (6), p.1138-1149 |
| issn | 0278-0070 1937-4151 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Automatic logic units Circuit faults Circuit simulation Computational efficiency Computer simulation Computing time Debugging Failure Fault diagnosis Faults Formal verification Hardware design languages Localization Position (location) Preprocessing Safety satisfiability checking sequential circuit fault diagnosis Sequential circuits |
| title | Automatic Fault Localization for Property Checking |
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