CHIPS: Custom Hardware Instruction Processor Synthesis

This paper describes an integer-linear-programming (ILP)-based system called custom hardware instruction processor synthesis (CHIPS) that identifies custom instructions for critical code segments, given the available data bandwidth and transfer latencies between custom logic and a baseline processor...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2008-03, Vol.27 (3), p.528-541
Hauptverfasser:	Atasu, K., Ozturan, C., Dundar, G., Mencer, O., Luk, W.
Format:	Artikel
Sprache:	eng
Schlagworte:	Application specific processors Application-specific instruction-set processors (ASIPs) Bandwidth Benchmarks Chips Costs custom instructions customizable processors Delay Design engineering extensible processors Hardware Instruction sets integer linear programming (ILP) Logic Microprocessors optimization algorithms Process design Registers Segments Synthesis Time to market
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