Transaction-Aware Network-on-Chip Resource Reservation

Performance and scalability are critically-important for on-chip interconnect in many-core chip-multiprocessor systems. Packet-switched interconnect fabric, widely viewed as the de facto on-chip data communication backplane in the many-core era, offers high throughput and excellent scalability. Howe...

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Veröffentlicht in:	IEEE computer architecture letters 2008-07, Vol.7 (2), p.53-56
Hauptverfasser:	Zheng Li, Changyun Zhu, Li Shang, Dick, R., Yihe Sun
Format:	Artikel
Sprache:	eng
Schlagworte:	Arbitration Backplanes Benchmarks Buffers Computer buffers Data communication Delay Fabrics Interconnection architectures Interconnections (Subsystems) Network-on-a-chip Networks On-chip interconnection networks Optimization Parallel Architectures Preserves Routers Run time (computers) Runtime Scalability System-on-a-chip Throughput
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