Process-Variation-Aware Adaptive Cache Architecture and Management

Fabricating circuits that employ ever-smaller transistors leads to dramatic variations in critical process parameters. This in turn results in large variations in execution/access latencies of different hardware components. This situation is even more severe for memory components due to minimum-size...

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Veröffentlicht in:	IEEE transactions on computers 2009-07, Vol.58 (7), p.865-877
Hauptverfasser:	Mutyam, M., Feng Wang, Krishnan, R., Narayanan, V., Kandemir, M., Yuan Xie, Irwin, M.J.
Format:	Artikel
Sprache:	eng
Schlagworte:	address prediction Benchmark testing cache Circuits Clocks Delay Hardware Management Nonuniform Pipelines Policies Process parameters Process variation Product development Semiconductor devices Studies superscalar processors Threshold voltage Timing Transistors
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