A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment
Gate sizing and threshold voltage (V t ) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven heuristics or based on discretizing continuous optimization solutions. Sensitivity-driven heuristics are easily trapped...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2010-02, Vol.29 (2), p.223-234 |
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| creator | Liu, Yifang Hu, Jiang |
| description | Gate sizing and threshold voltage (V t ) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven heuristics or based on discretizing continuous optimization solutions. Sensitivity-driven heuristics are easily trapped in local optima and the discretization may be subject to remarkable errors. In this paper, we propose a systematic combinatorial approach for simultaneous gate sizing and V t assignment. The core idea of this approach is joint relaxation and restriction, which employs consistency relaxation and coupled bi-directional solution search. The process of joint relaxation and restriction is conducted iteratively to systematically improve solutions. Our algorithm is compared with a state-of-the-art previous work on benchmark circuits. The results from our algorithm can lead to about 22% less power dissipation subject to the same timing constraints. |
| doi_str_mv | 10.1109/TCAD.2009.2035575 |
| format | Article |
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Existing methods, by and large, are either sensitivity-driven heuristics or based on discretizing continuous optimization solutions. Sensitivity-driven heuristics are easily trapped in local optima and the discretization may be subject to remarkable errors. In this paper, we propose a systematic combinatorial approach for simultaneous gate sizing and V t assignment. The core idea of this approach is joint relaxation and restriction, which employs consistency relaxation and coupled bi-directional solution search. The process of joint relaxation and restriction is conducted iteratively to systematically improve solutions. Our algorithm is compared with a state-of-the-art previous work on benchmark circuits. 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| source | IEEE Electronic Library (IEL) |
| subjects | Algorithms circuit optimization Circuits Combinatorial analysis Delay estimation Dynamic programming Gates (circuits) Heuristic Iterative algorithms Linear programming Mathematical models Optimization methods Power dissipation Sizing Table lookup Threshold voltage Time measurements Timing |
| title | A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment |
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