A −90-dBFS-IM3, −164-dBFS/Hz-NSD, 700-MHz-Bandwidth Continuous-Time Pipelined ADC With Digital Cancellation of DAC Errors
This paper describes a continuous-time (CT) pipelined analog-to-digital converter (ADC) that represents a technology push along both-third-order distortion and noise-dimensions. Distortion is tackled using on-chip digital cancellation of static and timing digital-to-analog converter (DAC) mismatch e...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2024-12, Vol.59 (12), p.4225-4236 |
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| container_title | IEEE journal of solid-state circuits |
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| creator | Patil, Sharvil Ganesan, Asha Shibata, Hajime Kozlov, Victor Taylor, Gerry Shrestha, Prawal Li, Zhao Lulec, Zeynep Vasilakopoulos, Konstantinos Theertham, Raviteja Paterson, Donald Yu, Qingnan Chowdhury, Aseer |
| description | This paper describes a continuous-time (CT) pipelined analog-to-digital converter (ADC) that represents a technology push along both-third-order distortion and noise-dimensions. Distortion is tackled using on-chip digital cancellation of static and timing digital-to-analog converter (DAC) mismatch errors. Low noise is achieved with design choices such as a resistive sub-DAC; a high-precision, on-chip, background-calibrated digital reconstruction filter (DRF); and a tunable LC lattice delay that allows a programmable sampling frequency. Implemented in a 16-nm FinFET process, the 6.4-GS/s prototype achieves an IM3 of −90 dBFS and a small-signal NSD of −164 dBFS/Hz over a 700-MHz bandwidth, while dissipating 703-mW power. Such performance makes it suitable for high-performance instrumentation and communications that demand robustness to large interferers while digitizing small signals. |
| doi_str_mv | 10.1109/JSSC.2024.3470516 |
| format | Article |
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Distortion is tackled using on-chip digital cancellation of static and timing digital-to-analog converter (DAC) mismatch errors. Low noise is achieved with design choices such as a resistive sub-DAC; a high-precision, on-chip, background-calibrated digital reconstruction filter (DRF); and a tunable LC lattice delay that allows a programmable sampling frequency. Implemented in a 16-nm FinFET process, the 6.4-GS/s prototype achieves an IM3 of −90 dBFS and a small-signal NSD of −164 dBFS/Hz over a 700-MHz bandwidth, while dissipating 703-mW power. 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| subjects | Analog to digital converters Analog-digital conversion Analog-to-digital converter (ADC) Background noise Bandwidths calibration complementary metal-oxide–semiconductor (CMOS) continuous time (CT) ADC CT pipelined (CTP) ADC Delays Digital to analog converters digitally assisted analog design Digitization Distortion Errors gigahertz data conversion high-speed ADC Impedance Low noise Noise Noise shaping noise-shaping ADC pipelined ADC Power dissipation Quantization (signal) Receivers System-on-chip Thermal stability |
| title | A −90-dBFS-IM3, −164-dBFS/Hz-NSD, 700-MHz-Bandwidth Continuous-Time Pipelined ADC With Digital Cancellation of DAC Errors |
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