A Two-Channel Interleaved ADC With Fast-Converging Foreground Time Calibration and Comparison-Based Control Logic
A dual-channel interleaved analog-to-digital converter (ADC) operating at 320 MS/s is prototyped to validate a fast-converging foreground time calibration algorithm that is independent of ADC offset errors. An input polarity switching technique is introduced to eliminate the impact of sub-ADC offset...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2024-11, Vol.32 (11), p.2001-2011 |
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| container_end_page | 2011 |
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| container_issue | 11 |
| container_start_page | 2001 |
| container_title | IEEE transactions on very large scale integration (VLSI) systems |
| container_volume | 32 |
| creator | Yan, Xiang Qin, Kefan Zheng, Xinyue Hu, Weibo Ma, Wei Cui, Haitao |
| description | A dual-channel interleaved analog-to-digital converter (ADC) operating at 320 MS/s is prototyped to validate a fast-converging foreground time calibration algorithm that is independent of ADC offset errors. An input polarity switching technique is introduced to eliminate the impact of sub-ADC offset mismatches during foreground time calibration. After foreground calibration, the signal-to-noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) are improved by 8.6 and 18.4 dB, respectively. In the sub-ADC design, a comparison functionality is enabled in the digital circuits to prevent metastability and expedite data conversion. The single-channel conversion rates reach 160 MS/s. The ADC is implemented via 40-nm digital CMOS technology, achieving a 52.01 dB signal-to-noise plus distortion ratio (SNDR) at near-Nyquist input while sampling at 320 MS/s. The overall power consumption is 3.65 mW, which includes an on-chip reference buffer and a clock circuit. |
| doi_str_mv | 10.1109/TVLSI.2024.3449293 |
| format | Article |
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| source | IEEE Electronic Library (IEL) |
| subjects | Algorithms Analog to digital converters Analog-to-digital converter (ADC) Calibration Clocks Convergence Data conversion Digital electronics Distortion foreground calibration Mathematical models Noise levels Power supplies Switches Switching (polarity) time-interleaved (TI) ADC timing-skew mismatch Very large scale integration Voltage |
| title | A Two-Channel Interleaved ADC With Fast-Converging Foreground Time Calibration and Comparison-Based Control Logic |
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