Design for Increased Defect Tolerance in Metamorphic GaAsP-on-Si Top Cells

To date, the greatest performance limiter in monolithic III-V/Si tandem (multijunction) solar cells, like GaAs_{0.75}P_{0.25}/Si, is excess threading dislocation densities (TDD) resulting from the lattice-mismatched heteroepitaxy. Recent developments in low-TDD GaAs y P 1- y /Si metamorphic buffers were used to grow standalone GaAs_{0.75}P_{0.25} top cells on Si with a TDD of 4 × 10 6 cm −2 , ∼2.5 × lower than previous iterations, greatly improving the potential for the production of high-efficiency tandems based on this platform. Nonetheless, these reduced-TDD cells were still found to possess considerable voltage-dependent carrier collection (VDC) losses. As such, to improve J SC and fill factor, without sacrificial reduction in V OC , a doping gradient within the cell base layer was designed and implemented. The updated design reduces VDC losses to levels that would otherwise require further TDD reduction by at least another 2.5 × (to ≤ 1.5 × 10 6 cm −2 ) in a typical flat doping profile design. Replacing the p + -Ga_{0.64}In_{0.36}P back surface field with p + -Al_{0.2}Ga_{0.8}As_{0.74}P_{0.26} provided an additional improvement in both V OC and J SC , yielding device performance equivalent to a 4 × TDD reduction in the previous design. The culmination of these design changes results in a new subcell that outperforms our previous best top cell by ∼4.3% absolute AM1.5G efficiency, with increases in fill factor, J SC , and W OC of about 3.3% absolute, 1.9 mA/cm 2 , and 0.12 V, respectively. This new design, coupled with the reduced TDD platform, paves a promising path toward the development of higher efficiency GaAs_{0.75}P_{0.25}